my current approach 
```rs
const STATUS_ADDR: u16 = 0x03; // Status register
const PORTA_ADDR:  u16 = 0x05; // Port A
const PORTB_ADDR:  u16 = 0x06; // Port B
const TRISA_ADDR:  u16 = 0x85; // Port A (Bank 1)
const TRISB_ADDR:  u16 = 0x86;

unsafe fn write_reg8(addr: u16, val: u8) {
    core::ptr::write_volatile(addr as *mut u8, val);
}

unsafe fn read_reg8(addr: u16) -> u8 {
    core::ptr::read_volatile(addr as *const u8)
}
```