"I have a small verilog file that..." <- > <@famubu:matrix.org> I have a small verilog file that I synthesized with yosys. > Yosys stat shows that some LUTs and a few registers are needed. > But when I used nextpnr, it finally says no LUTs are used in the utilization. > Could it be because I used a constraint file wrong or something? > I am trying a sipeed tang nano 9K. > Something is happening that is leading to the module I/O to be considered unreachable, and by extension your entire module. Check constraints