from amaranth import *
from amaranth.lib import io
from amaranth_boards.versa_ecp5 import VersaECP5Platform


def create_with_reset(reset_type):
    plat = VersaECP5Platform()
    led = io.Buffer('o', plat.request('led', dir='-'))

    m = Module()
    m.submodules += led
    if 'sync' in reset_type:
        clk_io = plat.request(plat.default_clk, dir="-")
        m.submodules.clk_buf = clk_buf = io.Buffer("i", clk_io)
        clk_i = clk_buf.i

        rst_io = plat.request(plat.default_rst, dir="-")
        m.submodules.rst_buf = rst_buf = io.Buffer("i", rst_io)
        rst_i = rst_buf.i

        m.domains += ClockDomain('sync', async_reset=(reset_type=='async'))
        m.d.comb += [
            ClockSignal('sync').eq(clk_i),
            ResetSignal('sync').eq(rst_i),
        ]

    s = Signal(init=1, name='signal_with_reset')
    
    m.d.sync += led.o.eq(s), s.eq(~s)
    plat.build(m, do_build=True)

create_with_reset('sgsr')
create_with_reset('sync')
create_with_reset('async')