I ported Google's Arm GICv3 driver to AArch32 (changing MSR/MRS to MCR/MCRR/MRC/MRRC) and then lost three hours of my life because I mis-typed 0b0100 as 8 instead of 4 and was writing to totally the wrong CP15 register.

But anyway, now you can have Software Generated Interrupts on a Cortex-R52:

```text
Creating GIC driver...
Calling git.setup()
Configure SGI
gic.enable_interrupt()
Enabling interrupts...
CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=0x1f }
CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=0x1f }
Send SGI
> IRQ
- IRQ handle SGI 3
< IRQ
```

Also I had a fun bug where my critical-section implementation got the interrupt state inverted, so every hprintln! would flip the interrupt mask status. That took quite a long time to figure out.