❯ : probe-rs --version
probe-rs 0.25.0 (git commit: 0b989aa)

~
❯ : probe-rs info
Available Probes:
0: STLink V3 -- 0483:3754:001800373432511330343838 (ST-LINK)
1: J-Link -- 1366:1024:000601006224 (J-Link)
Selection: 0
Probing target via JTAG

 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: JtagUnknownJtagChain
Error identifying target using protocol JTAG: An error with the usage of the probe occurred

Probing target via SWD

ARM Chip with debug port Default:
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR0 has invalid preamble (expected 0xd, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR2 has invalid preamble (expected 0x5, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR3 has invalid preamble (expected 0xb1, got 0x0)
Debug Port: DPv2, Designer: STMicroelectronics, Part: 0x4950, Revision: 0x0, Instance: 0x00
├── 0 MemoryAP (AmbaAhb3)
│   └── ROM Table (Class 1), Designer: STMicroelectronics
│       ├── Cortex-M4 SCS   (Generic IP component)
│       │   └── CPUID
│       │       ├── IMPLEMENTER: ARM Ltd
│       │       ├── VARIANT: 0
│       │       ├── PARTNO: Cortex-M4
│       │       └── REVISION: 1
│       ├── Cortex-M3 DWT   (Generic IP component)
│       ├── Cortex-M3 FBP   (Generic IP component)
│       ├── Cortex-M3 ITM   (Generic IP component)
│       ├── Cortex-M4 TPIU  (Coresight Component)
│       ├── Cortex-M4 ETM   (Coresight Component)
│       └── Coresight Component, Part: 0x0906, Devtype: 0x14, Archid: 0x0000, Designer: ARM Ltd
└── 1 MemoryAP (AmbaAhb3)
    └── Generic


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.


~
❯ : probe-rs info
Available Probes:
0: STLink V3 -- 0483:3754:001800373432511330343838 (ST-LINK)
1: J-Link -- 1366:1024:000601006224 (J-Link)
Selection: 1
Probing target via JTAG

ERROR probe_rs::probe::common: Fewer IRs detected than TAPs
Error identifying target using protocol JTAG: An error with the usage of the probe occurred

Probing target via SWD

ARM Chip with debug port Default:
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR0 has invalid preamble (expected 0xd, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR2 has invalid preamble (expected 0x5, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR3 has invalid preamble (expected 0xb1, got 0x0)
Debug Port: DPv2, Designer: STMicroelectronics, Part: 0x4950, Revision: 0x0, Instance: 0x00
├── 0 MemoryAP (AmbaAhb3)
│   └── ROM Table (Class 1), Designer: STMicroelectronics
│       ├── Cortex-M4 SCS   (Generic IP component)
│       │   └── CPUID
│       │       ├── IMPLEMENTER: ARM Ltd
│       │       ├── VARIANT: 0
│       │       ├── PARTNO: Cortex-M4
│       │       └── REVISION: 1
│       ├── Cortex-M3 DWT   (Generic IP component)
│       ├── Cortex-M3 FBP   (Generic IP component)
│       ├── Cortex-M3 ITM   (Generic IP component)
│       ├── Cortex-M4 TPIU  (Coresight Component)
│       ├── Cortex-M4 ETM   (Coresight Component)
│       └── Coresight Component, Part: 0x0906, Devtype: 0x14, Archid: 0x0000, Designer: ARM Ltd
└── 1 MemoryAP (AmbaAhb3)
    └── Generic


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.