* ```     Running `target/debug/probe-rs info`
Probing target via JTAG
-----------------------

 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: JtagNoDeviceConnected
Failed to identify target using protocol JTAG: An error with the usage of the probe occurred

Caused by:
    0: An error which is specific to the debug probe in use occurred.
    1: Command failed with status JtagNoDeviceConnected.

Probing target via SWD
----------------------

 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: SwdApFault
ERROR probe_rs::architecture::arm::memory::romtable: 	Failed to read component information at 0x0.
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e3000: CIDR0 has invalid preamble (expected 0xd, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e3000: CIDR2 has invalid preamble (expected 0x5, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e3000: CIDR3 has invalid preamble (expected 0xb1, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e4000: CIDR0 has invalid preamble (expected 0xd, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e4000: CIDR2 has invalid preamble (expected 0x5, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xe00e4000: CIDR3 has invalid preamble (expected 0xb1, got 0x0)
 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: SwdApFault
ERROR probe_rs::architecture::arm::memory::romtable: 	Failed to read component information at 0xe00f0000.
ARM Chip with debug port Default:

Debug Port: DPv2, Designer: STMicroelectronics, Part: 0x4500, Revision: 0x0, Instance: 0x00
├── V1(0) MemoryAP
│   └── 0 MemoryAP (AmbaAhb3)
│       ├── 0xe00fe000 ROM Table (Class 1), Designer: STMicroelectronics
│       ├── 0xe00ff000 ROM Table (Class 1), Designer: ARM Ltd
│       ├── 0xe0041000 ETM architecture (Coresight Component)
│       └── 0xe0043000 Coresight Component, Part: 0x0906, Devtype: 0x14, Archid: 0x0000, Designer: ARM Ltd
├── V1(1) MemoryAP
│   └── 1 MemoryAP (AmbaAhb3)
├── V1(2) MemoryAP
│   └── 2 MemoryAP (AmbaApb2Apb3)
│       ├── 0xe00e0000 ROM Table (Class 1), Designer: STMicroelectronics
│       ├── 0xe00e3000 Generic
│       ├── 0xe00e4000 Generic
│       └── 0xe00e5000 System TSGEN    (Core Link / Prime Cell / System component)
└── V1(3) Unknown AP (Designer: <unknown>, Class: Undefined, Type: 0x0, Variant: 0x0, Revision: 0x2)```