This is the ADC configuration:
```
 self.inner.cfgr1().modify(|_, w| {
            w.exten().rising_edge();
            // TIM6 TRG0
            unsafe { w.extsel().bits(0b101) };
            w.res().bits12();
            w.chselrmod().bit_per_input();
            w.dmacfg().circular();
            w.dmaen().enabled();
            w
        });
        self.inner.cfgr2().modify(|_, w| w.lftrig().enabled());
        self.inner.smpr().modify(|_, w| w.smp1().cycles160_5());
        self.inner.chselr1().write(|w| unsafe { w.bits(CHANNELS) });
        self.inner.ccr().modify(|_, w| {
            w.presc().div8();
            w.vrefen().enabled();
            w
        });

        self.inner.cr().modify(|_, w| w.advregen().enabled());
        // Give the voltage regulator some time to start
        asm::delay(20_000);

        while self.inner.isr().read().ccrdy().is_not_complete() {}
        self.inner.isr().write(|w| w.ccrdy().clear());