I have a bit of a problem:

I would like to control an external IC using an amaranth design. The vhdl implementation that I've based my design on uses DDR Buffers to offset the signals to the falling edge so that there are no problems with setup/hold times.

I would also like to simulate my design and check, that the output matches what I expect. However the DDR buffer docs explicitly mention that simulating them is currently not possible. Another way would be to use an FFBuffer with a falling edge trigger, something that the docs also state is currently not possible.

What would be the recommended way to "fix" this?