```rust
/// MMU Level 1 Page table.
///
/// 4096 entries, each covering 1MB
///
static mut MMU_L1_PAGE_TABLE: L1Table = L1Table([0; NUM_L1_PAGE_TABLE_ENTRIES]);

#[unsafe(no_mangle)]
pub unsafe extern "C" fn init_mmu_table() {
    let mut offset = 0;
    let mut addr = 0;

    unsafe {
        // The first entry (1 MB) is related to special DDR memory. See p.101 of the TMR.
        // We set is separtely to accomodate for future changes.
        MMU_L1_PAGE_TABLE.0[0] = L1Section::new(addr, SECTION_ATTRS_DDR).0;
        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_DDR_FULL_ACCESSIBLE] {
            *entry = L1Section::new(addr, SECTION_ATTRS_DDR).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_DDR_FULL_ACCESSIBLE;

        // 2 FPGA slaves.
        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_FPGA_SLAVE * 2] {
            *entry = L1Section::new(addr, SECTION_ATTRS_FPGA_SLAVES).0;
            addr += ONE_MB as u32;
        }
        offset += 2 * SEGMENTS_FPGA_SLAVE;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_0] {
            *entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_UNASSIGNED_0;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_IO_PERIPHS] {
            *entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_IO_PERIPHS;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_NAND] {
            *entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_NAND;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_NOR] {
            *entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_NOR;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_SRAM] {
            *entry = L1Section::new(addr, SECTION_ATTRS_SRAM).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_SRAM;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_1] {
            *entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_UNASSIGNED_1;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_AMBA_APB] {
            *entry = L1Section::new(addr, SECTION_ATTRS_SHAREABLE_DEVICE).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_AMBA_APB;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_2] {
            *entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_UNASSIGNED_2;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_QSPI_XIP] {
            *entry = L1Section::new(addr, SECTION_ATTRS_QSPI_XIP).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_QSPI_XIP;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_UNASSIGNED_3] {
            *entry = L1Section::new(addr, SECTION_ATTRS_UNASSIGNED_RESERVED).0;
            addr += ONE_MB as u32;
        }
        offset += SEGMENTS_UNASSIGNED_3;

        for entry in &mut MMU_L1_PAGE_TABLE.0[offset..offset + SEGMENTS_OCM_MAPPED_HIGH] {
            *entry = L1Section::new(addr, SECTION_ATTRS_OCM_MAPPED_HIGH).0;
            addr += ONE_MB as u32;
        }
    }
}
```

basically I am trying to do this code compile time