Max[m]: but i do get this output of course:
```
probe-rs info --chip STM32H747XI
Probing target via JTAG

 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: JtagNoDeviceConnected
Error identifying target using protocol JTAG: An error with the usage of the probe occurred

Probing target via SWD

ARM Chip with debug port Default:
 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: SwdApWdataError
 WARN probe_rs::probe::stlink: send_jtag_command 242 failed: SwdApWdataError
Debug Port: DPv2, Designer: STMicroelectronics, Part: 0x4500, Revision: 0x0, Instance: 0x00
├── 0 MemoryAP (AmbaAhb3)
│   └── ROM Table (Class 1), Designer: STMicroelectronics
│       ├── ROM Table (Class 1), Designer: ARM Ltd
│       │   ├── Cortex-M4 SCS   (Generic IP component)
│       │   │   └── CPUID
│       │   │       ├── IMPLEMENTER: ARM Ltd
│       │   │       ├── VARIANT: 1
│       │   │       ├── PARTNO: Cortex-M7
│       │   │       └── REVISION: 1
│       │   ├── Cortex-M3 DWT   (Generic IP component)
│       │   ├── Cortex-M7 FBP   (Generic IP component)
│       │   └── Cortex-M3 ITM   (Generic IP component)
│       ├── Cortex-M7 ETM   (Coresight Component)
│       └── Coresight Component, Part: 0x0906, Devtype: 0x14, Archid: 0x0000, Designer: ARM Ltd
├── 1 MemoryAP (AmbaAhb3)
│   └── Error during access: The debug probe encountered an error.
├── 2 MemoryAP (AmbaApb2Apb3)
│   └── Error during access: The debug probe encountered an error.
└── 3 Unknown AP (Designer: <unknown>, Class: Undefined, Type: 0x0, Variant: 0x0, Revision: 0x2)


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.
```