```from amaranth import *
from amaranth.lib import *
class clockdivider(wiring.Component):
    clkout: wiring.Out(1)
    clkiin: wiring.In(1)
    def elaborate(self,platform):
        m= Module()
        half_freq = int(platform.default_clk_period.hertz // 2)
        timer = Signal(range(half_freq+1))
        with m.If(timer== half_freq):
            m.d.sync += clkout.o.eq(~clkout.o)
            m.d.sync += timer.eq(0)
        with m.Else():
            m.d.sync += timer.eq(timer + 1)
        return m``` this is what I have , "based "on the tutorial from the docs