Probing target via JTAG

ERROR probe_rs::probe::common: Fewer IRs detected than TAPs
Error identifying target using protocol JTAG: An error with the usage of the probe occurred

Probing target via SWD

ARM Chip with debug port Default:
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR0 has invalid preamble (expected 0xd, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR2 has invalid preamble (expected 0x5, got 0x0)
 WARN probe_rs::architecture::arm::memory::romtable: Component at 0xf0000000: CIDR3 has invalid preamble (expected 0xb1, got 0x0)
Debug Port: DPv2, Designer: STMicroelectronics, Part: 0x4950, Revision: 0x0, Instance: 0x00
├── Memory AP is not accessible, DeviceEn bit not set
└── 1 MemoryAP (AmbaAhb3)
    └── 0xf0000000 Generic


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.