W: glasgow.support.plugin: loading out-of-tree plugin 'glasgowcontrib-applet-mu'; plugin API is currently unstable and subject to change without warning I: glasgow.hardware.device: generating bitstream ID 26c180542773b2064dd410c405ebe8d9 I: glasgow.hardware.build_plan: build: + '[' -n '' ']' I: glasgow.hardware.build_plan: build: + : /home/galibert/.local/pipx/venvs/glasgow/bin/yowasp-yosys I: glasgow.hardware.build_plan: build: + : /home/galibert/.local/pipx/venvs/glasgow/bin/yowasp-nextpnr-ice40 I: glasgow.hardware.build_plan: build: + : /home/galibert/.local/pipx/venvs/glasgow/bin/yowasp-icepack I: glasgow.hardware.build_plan: build: + /home/galibert/.local/pipx/venvs/glasgow/bin/yowasp-yosys -l top.rpt top.ys I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: /----------------------------------------------------------------------------\ I: glasgow.hardware.build_plan: build: | yosys -- Yosys Open SYnthesis Suite | I: glasgow.hardware.build_plan: build: | Copyright (C) 2012 - 2025 Claire Xenia Wolf | I: glasgow.hardware.build_plan: build: | Distributed under an ISC-like license, type "license" to see terms | I: glasgow.hardware.build_plan: build: \----------------------------------------------------------------------------/ I: glasgow.hardware.build_plan: build: Yosys 0.53 (git sha1 53c22ab7c, ccache clang 18.1.3 -O3 -flto -flto) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: -- Executing script file `top.ys' -- I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 1. Executing RTLIL frontend. I: glasgow.hardware.build_plan: build: Input filename: top.il I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2. Executing SYNTH_ICE40 pass. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.1. Executing Verilog-2005 frontend: /share/ice40/cells_sim.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/cells_sim.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_IO'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_GB_IO'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_GB'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_LUT4'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_CARRY'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFF'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFE'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFSR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFSS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFESR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFER'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFESS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFES'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFN'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNE'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNSR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNSS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNESR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNER'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNESS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_DFFNES'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RAM40_4K'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RAM40_4KNR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RAM40_4KNW'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\ICESTORM_LC'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_PLL40_CORE'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_PLL40_PAD'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_PLL40_2_PAD'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_WARMBOOT'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_SPRAM256KA'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_HFOSC'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_LFOSC'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RGBA_DRV'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_LED_DRV_CUR'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_RGB_DRV'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_I2C'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_SPI'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_LEDDA_IP'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_FILTER_50NS'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_IO_I3C'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_IO_OD'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\SB_MAC16'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\ICESTORM_RAM'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.2. Executing HIERARCHY pass (managing design hierarchy). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.2.1. Analyzing design hierarchy.. I: glasgow.hardware.build_plan: build: Top module: \top I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_4 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_4.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_3 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_3.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_2 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_2.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_1 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_1.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_0 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_0.buf I: glasgow.hardware.build_plan: build: Used module: \top.cd_sync I: glasgow.hardware.build_plan: build: Used module: \top.cd_sync.clk_buf I: glasgow.hardware.build_plan: build: Used module: \top.U$18 I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_balls I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0.io I: glasgow.hardware.build_plan: build: Used module: \top.in_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.in_fifo_0.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid.skid.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid.skid.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.in_fifo_1 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.in_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.flag$40 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.fd I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.pktend I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.slwr$37 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.slrd$36 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.sloe$35 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.fifoadr I: glasgow.hardware.build_plan: build: Used module: \top.i2c_registers I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.U$3 I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.U$2 I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.io_sda I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.io_scl I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.2.2. Analyzing design hierarchy.. I: glasgow.hardware.build_plan: build: Top module: \top I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_4 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_4.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_3 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_3.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_2 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_2.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_1 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_1.buf I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_0 I: glasgow.hardware.build_plan: build: Used module: \top.pin_led_0.buf I: glasgow.hardware.build_plan: build: Used module: \top.cd_sync I: glasgow.hardware.build_plan: build: Used module: \top.cd_sync.clk_buf I: glasgow.hardware.build_plan: build: Used module: \top.U$18 I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.data_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.lr_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer.oe I: glasgow.hardware.build_plan: build: Used module: \top.U$18.clk_buffer.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_balls I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_12.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_11.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_10.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_9.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_8.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_7.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_6.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_5.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_4.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_3.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_2.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_1.io I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0.oe$10 I: glasgow.hardware.build_plan: build: Used module: \top.unused_pin_0.io I: glasgow.hardware.build_plan: build: Used module: \top.in_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.in_fifo_0.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_1.skid.skid.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid.skid I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.out_fifo_0.skid.skid.inner I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.in_fifo_1 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.in_fifo_0 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.flag$40 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.fd I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.pktend I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.slwr$37 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.slrd$36 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.sloe$35 I: glasgow.hardware.build_plan: build: Used module: \top.fx2_crossbar.bus.fifoadr I: glasgow.hardware.build_plan: build: Used module: \top.i2c_registers I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.U$3 I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.U$2 I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.io_sda I: glasgow.hardware.build_plan: build: Used module: \top.i2c_target.bus.io_scl I: glasgow.hardware.build_plan: build: Removed 0 unused modules. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3. Executing PROC pass (convert processes to netlists). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.i2c_target.$79'. I: glasgow.hardware.build_plan: build: Cleaned up 1 empty switch. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $10 in module top.cd_sync. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $49 in module top.U$18. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $50 in module top.fx2_crossbar.out_fifo_1.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $48 in module top.fx2_crossbar.out_fifo_1.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $46 in module top.fx2_crossbar.out_fifo_1.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $9 in module top.fx2_crossbar.out_fifo_1.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $8 in module top.fx2_crossbar.out_fifo_1.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $6 in module top.fx2_crossbar.out_fifo_1.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $50 in module top.fx2_crossbar.out_fifo_0.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $48 in module top.fx2_crossbar.out_fifo_0.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $46 in module top.fx2_crossbar.out_fifo_0.skid.skid.inner. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $9 in module top.fx2_crossbar.out_fifo_0.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $8 in module top.fx2_crossbar.out_fifo_0.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $6 in module top.fx2_crossbar.out_fifo_0.skid. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $13 in module top.fx2_crossbar.in_fifo_1. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $11 in module top.fx2_crossbar.in_fifo_1. I: glasgow.hardware.build_plan: build: Marked 3 switch rules as full_case in process $105 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $103 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $99 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 2 switch rules as full_case in process $95 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $94 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $92 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $90 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $88 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $85 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $82 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $81 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $79 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $77 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $69 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $66 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $65 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $63 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $61 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $56 in module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $24 in module top.i2c_registers. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $20 in module top.i2c_registers. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $16 in module top.i2c_registers. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $13 in module top.i2c_registers. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $88 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Removed 1 dead cases from process $85 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $85 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Removed 1 dead cases from process $77 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Marked 1 switch rules as full_case in process $77 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Removed 1 dead cases from process $71 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Marked 3 switch rules as full_case in process $71 in module top.i2c_target. I: glasgow.hardware.build_plan: build: Removed a total of 3 dead cases. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). I: glasgow.hardware.build_plan: build: Removed 37 redundant assignments. I: glasgow.hardware.build_plan: build: Promoted 2 assignments to connections. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.4. Executing PROC_INIT pass (extract init attributes). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.5. Executing PROC_ARST pass (detect async resets in processes). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). I: glasgow.hardware.build_plan: build: Converted 1 switch. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.cd_sync.$10'. I: glasgow.hardware.build_plan: build: 1/1: $4 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.cd_sync.$8'. I: glasgow.hardware.build_plan: build: 1/1: $3 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$55'. I: glasgow.hardware.build_plan: build: 1/1: \o_stream__valid I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$53'. I: glasgow.hardware.build_plan: build: 1/1: $20 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$51'. I: glasgow.hardware.build_plan: build: 1/1: $19 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$49'. I: glasgow.hardware.build_plan: build: 1/1: $18 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$47'. I: glasgow.hardware.build_plan: build: 1/1: $17 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$45'. I: glasgow.hardware.build_plan: build: 1/1: $16 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$43'. I: glasgow.hardware.build_plan: build: 1/1: $15 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$41'. I: glasgow.hardware.build_plan: build: 1/1: $14 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$39'. I: glasgow.hardware.build_plan: build: 1/1: $13 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$37'. I: glasgow.hardware.build_plan: build: 1/1: $12 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$35'. I: glasgow.hardware.build_plan: build: 1/1: $11 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$33'. I: glasgow.hardware.build_plan: build: 1/1: $10 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$31'. I: glasgow.hardware.build_plan: build: 1/1: $9 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.U$18.$29'. I: glasgow.hardware.build_plan: build: 1/1: $8 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.in_fifo_0.inner.$77'. I: glasgow.hardware.build_plan: build: 1/1: $33 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.in_fifo_0.inner.$75'. I: glasgow.hardware.build_plan: build: 1/1: $32 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.in_fifo_0.inner.$73'. I: glasgow.hardware.build_plan: build: 1/1: $31 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.in_fifo_0.inner.$71'. I: glasgow.hardware.build_plan: build: 1/1: $30 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: 1/1: $21 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: 1/1: $20 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: 1/1: $19 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.$9'. I: glasgow.hardware.build_plan: build: 1/1: \i__ready I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.$8'. I: glasgow.hardware.build_plan: build: 1/1: \o__valid$9 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.$7'. I: glasgow.hardware.build_plan: build: 1/1: \o__ready$8 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_1.skid.$6'. I: glasgow.hardware.build_plan: build: 1/1: \o__payload I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: 1/1: $21 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: 1/1: $20 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: 1/1: $19 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.$9'. I: glasgow.hardware.build_plan: build: 1/1: \i__ready I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.$8'. I: glasgow.hardware.build_plan: build: 1/1: \o__valid$9 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.$7'. I: glasgow.hardware.build_plan: build: 1/1: \o__ready$8 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.out_fifo_0.skid.$6'. I: glasgow.hardware.build_plan: build: 1/1: \o__payload I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.in_fifo_1.$13'. I: glasgow.hardware.build_plan: build: 1/1: $5 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.in_fifo_1.$11'. I: glasgow.hardware.build_plan: build: 1/1: $4 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.in_fifo_0.$13'. I: glasgow.hardware.build_plan: build: 1/1: $5 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.in_fifo_0.$11'. I: glasgow.hardware.build_plan: build: 1/1: $4 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$48'. I: glasgow.hardware.build_plan: build: 1/1: $7 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$46'. I: glasgow.hardware.build_plan: build: 1/1: $6 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$44'. I: glasgow.hardware.build_plan: build: 1/1: $5 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$42'. I: glasgow.hardware.build_plan: build: 1/1: $4 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$40'. I: glasgow.hardware.build_plan: build: 1/1: $3 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$38'. I: glasgow.hardware.build_plan: build: 1/1: $2 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.bus.$37'. I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$105'. I: glasgow.hardware.build_plan: build: 1/1: $38 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$103'. I: glasgow.hardware.build_plan: build: 1/1: $37 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$101'. I: glasgow.hardware.build_plan: build: 1/1: $36 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$99'. I: glasgow.hardware.build_plan: build: 1/1: $35 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$98'. I: glasgow.hardware.build_plan: build: 1/1: \slrd I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$97'. I: glasgow.hardware.build_plan: build: 1/1: \pend I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$96'. I: glasgow.hardware.build_plan: build: 1/1: \slwr I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$95'. I: glasgow.hardware.build_plan: build: 1/1: \w__valid$53 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$94'. I: glasgow.hardware.build_plan: build: 1/1: \w__valid$52 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$93'. I: glasgow.hardware.build_plan: build: 1/1: \nrdy_i I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$92'. I: glasgow.hardware.build_plan: build: 1/1: \flushed$49 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$91'. I: glasgow.hardware.build_plan: build: 1/1: \flushed I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$90'. I: glasgow.hardware.build_plan: build: 1/1: \in_eps__1__data__ready I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$89'. I: glasgow.hardware.build_plan: build: 1/1: \in_eps__0__data__ready I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$88'. I: glasgow.hardware.build_plan: build: 1/1: \w__payload$43 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$87'. I: glasgow.hardware.build_plan: build: 1/1: \w__payload$42 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$85'. I: glasgow.hardware.build_plan: build: 1/1: $33 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$82'. I: glasgow.hardware.build_plan: build: 1/1: $30 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$81'. I: glasgow.hardware.build_plan: build: 1/1: $29 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$79'. I: glasgow.hardware.build_plan: build: 1/1: $27 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$77'. I: glasgow.hardware.build_plan: build: 1/1: $25 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$69'. I: glasgow.hardware.build_plan: build: 1/1: $17 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$66'. I: glasgow.hardware.build_plan: build: 1/1: $14 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$65'. I: glasgow.hardware.build_plan: build: 1/1: $13 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$63'. I: glasgow.hardware.build_plan: build: 1/1: $11 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$61'. I: glasgow.hardware.build_plan: build: 1/1: $9 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.fx2_crossbar.$56'. I: glasgow.hardware.build_plan: build: 1/1: \data__o I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$24'. I: glasgow.hardware.build_plan: build: 1/1: $9 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$22'. I: glasgow.hardware.build_plan: build: 1/1: $8 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$20'. I: glasgow.hardware.build_plan: build: 1/1: $7 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$18'. I: glasgow.hardware.build_plan: build: 1/1: $6 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$16'. I: glasgow.hardware.build_plan: build: 1/1: $5 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$14'. I: glasgow.hardware.build_plan: build: 1/1: $4 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$13'. I: glasgow.hardware.build_plan: build: 1/1: \ack_o I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_registers.$11'. I: glasgow.hardware.build_plan: build: 1/1: $2 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.bus.$23'. I: glasgow.hardware.build_plan: build: 1/1: $8 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.bus.$21'. I: glasgow.hardware.build_plan: build: 1/1: $7 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$90'. I: glasgow.hardware.build_plan: build: 1/1: \read I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$89'. I: glasgow.hardware.build_plan: build: 1/1: \restart I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$88'. I: glasgow.hardware.build_plan: build: 1/1: \stop I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$87'. I: glasgow.hardware.build_plan: build: 1/1: \start I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$85'. I: glasgow.hardware.build_plan: build: 1/1: $39 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$83'. I: glasgow.hardware.build_plan: build: 1/1: $38 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$81'. I: glasgow.hardware.build_plan: build: 1/1: $37 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$79'. I: glasgow.hardware.build_plan: build: 1/1: $36 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$77'. I: glasgow.hardware.build_plan: build: 1/1: $35 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$75'. I: glasgow.hardware.build_plan: build: 1/1: $34 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$73'. I: glasgow.hardware.build_plan: build: 1/1: $33 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.i2c_target.$71'. I: glasgow.hardware.build_plan: build: 1/1: $32 I: glasgow.hardware.build_plan: build: Creating decoders for process `\top.$1'. I: glasgow.hardware.build_plan: build: 1/1: \applet0_rst I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.cd_sync.$10'. I: glasgow.hardware.build_plan: build: Removing empty process `top.cd_sync.$10'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.cd_sync.$8'. I: glasgow.hardware.build_plan: build: Removing empty process `top.cd_sync.$8'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.U$18.$55'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$55'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.U$18.$53'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$53'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.U$18.$51'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$51'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.U$18.$49'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$49'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.U$18.$47'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$47'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$45'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$45'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$43'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$43'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$41'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$41'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$39'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$39'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$37'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$37'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$35'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$35'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$33'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$33'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$31'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$31'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.U$18.$29'. I: glasgow.hardware.build_plan: build: Removing empty process `top.U$18.$29'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.in_fifo_0.inner.$77'. I: glasgow.hardware.build_plan: build: Removing empty process `top.in_fifo_0.inner.$77'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.in_fifo_0.inner.$75'. I: glasgow.hardware.build_plan: build: Removing empty process `top.in_fifo_0.inner.$75'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.in_fifo_0.inner.$73'. I: glasgow.hardware.build_plan: build: Removing empty process `top.in_fifo_0.inner.$73'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.in_fifo_0.inner.$71'. I: glasgow.hardware.build_plan: build: Removing empty process `top.in_fifo_0.inner.$71'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.out_fifo_1.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_1.skid.$9'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.$9'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_1.skid.$8'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.$8'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_1.skid.$7'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.$7'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_1.skid.$6'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_1.skid.$6'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.skid.inner.$50'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.skid.inner.$48'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.out_fifo_0.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.skid.inner.$46'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_0.skid.$9'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.$9'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_0.skid.$8'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.$8'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_0.skid.$7'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.$7'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.out_fifo_0.skid.$6'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.out_fifo_0.skid.$6'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.fx2_crossbar.in_fifo_1.$13'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.in_fifo_1.$13'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.in_fifo_1.$11'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.in_fifo_1.$11'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.fx2_crossbar.in_fifo_0.$13'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.in_fifo_0.$13'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.in_fifo_0.$11'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.in_fifo_0.$11'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$48'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$48'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$46'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$46'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$44'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$44'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$42'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$42'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$40'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$40'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.bus.$38'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$38'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.bus.$37'. I: glasgow.hardware.build_plan: build: Found and cleaned up 6 empty switches in `\top.fx2_crossbar.$105'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$105'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.$103'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$103'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.$101'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$101'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.fx2_crossbar.$99'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$99'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$98'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$98'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$97'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$97'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$96'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$96'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$95'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$95'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$94'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$94'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$93'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$93'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$92'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$92'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$91'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$91'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$90'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$90'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.fx2_crossbar.$89'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$89'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$88'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$88'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$87'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$87'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$85'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$85'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$82'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$82'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$81'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$81'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$79'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$79'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$77'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$77'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$69'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$69'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$66'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$66'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$65'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$65'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$63'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$63'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$61'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$61'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.fx2_crossbar.$56'. I: glasgow.hardware.build_plan: build: Removing empty process `top.fx2_crossbar.$56'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_registers.$24'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$24'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_registers.$22'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$22'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_registers.$20'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$20'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.i2c_registers.$18'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$18'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_registers.$16'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$16'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.i2c_registers.$14'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$14'. I: glasgow.hardware.build_plan: build: Found and cleaned up 3 empty switches in `\top.i2c_registers.$13'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$13'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.i2c_registers.$11'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_registers.$11'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.i2c_target.bus.$23'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.bus.$23'. I: glasgow.hardware.build_plan: build: Found and cleaned up 1 empty switch in `\top.i2c_target.bus.$21'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.bus.$21'. I: glasgow.hardware.build_plan: build: Found and cleaned up 5 empty switches in `\top.i2c_target.$90'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$90'. I: glasgow.hardware.build_plan: build: Found and cleaned up 6 empty switches in `\top.i2c_target.$89'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$89'. I: glasgow.hardware.build_plan: build: Found and cleaned up 8 empty switches in `\top.i2c_target.$88'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$88'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_target.$87'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$87'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_target.$85'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$85'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_target.$83'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$83'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_target.$81'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$81'. I: glasgow.hardware.build_plan: build: Found and cleaned up 7 empty switches in `\top.i2c_target.$79'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$79'. I: glasgow.hardware.build_plan: build: Found and cleaned up 13 empty switches in `\top.i2c_target.$77'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$77'. I: glasgow.hardware.build_plan: build: Found and cleaned up 4 empty switches in `\top.i2c_target.$75'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$75'. I: glasgow.hardware.build_plan: build: Found and cleaned up 6 empty switches in `\top.i2c_target.$73'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$73'. I: glasgow.hardware.build_plan: build: Found and cleaned up 18 empty switches in `\top.i2c_target.$71'. I: glasgow.hardware.build_plan: build: Removing empty process `top.i2c_target.$71'. I: glasgow.hardware.build_plan: build: Found and cleaned up 2 empty switches in `\top.$1'. I: glasgow.hardware.build_plan: build: Removing empty process `top.$1'. I: glasgow.hardware.build_plan: build: Cleaned up 247 empty switches. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.3.12. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_4.buf. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_4. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_3.buf. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_3. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_2.buf. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_2. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_1.buf. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_1. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_0.buf. I: glasgow.hardware.build_plan: build: Optimizing module top.pin_led_0. I: glasgow.hardware.build_plan: build: Optimizing module top.cd_sync.clk_buf. I: glasgow.hardware.build_plan: build: Optimizing module top.cd_sync. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.data_buffer.oe. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.data_buffer.io. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.data_buffer. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.lr_buffer.oe. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.lr_buffer.io. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.lr_buffer. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.clk_buffer.oe. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.clk_buffer.io. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18.clk_buffer. I: glasgow.hardware.build_plan: build: Optimizing module top.U$18. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.unused_balls. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_12.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_12.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_12. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_11.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_11.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_11. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_10.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_10.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_9.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_9.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_9. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_8.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_8.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_8. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_7.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_7.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_7. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_6.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_6.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_6. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_5.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_5.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_5. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_4.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_4.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_4. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_3.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_3.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_3. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_2.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_2.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_2. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_1.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_1.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_1. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_0.oe$10. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_0.io. I: glasgow.hardware.build_plan: build: Optimizing module top.unused_pin_0. I: glasgow.hardware.build_plan: build: Optimizing module top.in_fifo_0.inner. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.in_fifo_0. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_1.skid.skid.inner. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_1.skid.skid. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_1.skid. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_1. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_0.skid.skid.inner. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_0.skid.skid. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_0.skid. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.out_fifo_0. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.in_fifo_1. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.in_fifo_0. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.flag$40. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.fd. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.pktend. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.slwr$37. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.slrd$36. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.sloe$35. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus.fifoadr. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar.bus. I: glasgow.hardware.build_plan: build: Optimizing module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_registers. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target.bus.U$3. I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target.bus.U$2. I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target.bus.io_sda. I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target.bus.io_scl. I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target.bus. I: glasgow.hardware.build_plan: build: Optimizing module top.i2c_target. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.4. Executing FLATTEN pass (flatten design). I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_4.buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_4. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_3.buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_3. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_2.buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_2. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_1.buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_1. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_0.buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.pin_led_0. I: glasgow.hardware.build_plan: build: Deleting now unused module top.cd_sync.clk_buf. I: glasgow.hardware.build_plan: build: Deleting now unused module top.cd_sync. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.data_buffer.oe. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.data_buffer.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.data_buffer. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.lr_buffer.oe. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.lr_buffer.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.lr_buffer. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.clk_buffer.oe. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.clk_buffer.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18.clk_buffer. I: glasgow.hardware.build_plan: build: Deleting now unused module top.U$18. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_balls. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_12.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_12.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_12. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_11.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_11.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_11. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_10.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_10.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_9.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_9.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_9. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_8.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_8.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_8. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_7.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_7.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_7. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_6.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_6.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_6. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_5.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_5.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_5. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_4.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_4.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_4. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_3.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_3.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_3. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_2.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_2.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_2. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_1.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_1.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_1. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_0.oe$10. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_0.io. I: glasgow.hardware.build_plan: build: Deleting now unused module top.unused_pin_0. I: glasgow.hardware.build_plan: build: Deleting now unused module top.in_fifo_0.inner. I: glasgow.hardware.build_plan: build: Deleting now unused module top.in_fifo_0. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_1.skid.skid.inner. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_1.skid.skid. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_1.skid. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_1. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_0.skid.skid.inner. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_0.skid.skid. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_0.skid. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.out_fifo_0. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.in_fifo_1. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.in_fifo_0. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.flag$40. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.fd. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.pktend. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.slwr$37. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.slrd$36. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.sloe$35. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus.fifoadr. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar.bus. I: glasgow.hardware.build_plan: build: Deleting now unused module top.fx2_crossbar. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_registers. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target.bus.U$3. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target.bus.U$2. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target.bus.io_sda. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target.bus.io_scl. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target.bus. I: glasgow.hardware.build_plan: build: Deleting now unused module top.i2c_target. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.5. Executing TRIBUF pass. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.6. Executing DEMINOUT pass (demote inout ports to input or output). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.7. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 145 unused cells and 647 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.9. Executing CHECK pass (checking for obvious problems). I: glasgow.hardware.build_plan: build: Checking module top... I: glasgow.hardware.build_plan: build: Found and reported 0 problems. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 68 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\fx2_crossbar.$procmux$617: $auto$opt_reduce.cc:137:opt_pmux$1172 I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\fx2_crossbar.$procmux$632: $auto$opt_reduce.cc:137:opt_pmux$1174 I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 2 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 19 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 0 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 1 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 2 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 3 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 4 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 5 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 6 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 7 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 8 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 9 on $flatten\fx2_crossbar.\in_fifo_1.$12 ($dff) from module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 164 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$770: { $auto$opt_reduce.cc:137:opt_pmux$1176 $flatten\i2c_target.$procmux$1004_CMP } I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$946: $auto$opt_reduce.cc:137:opt_pmux$1178 I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$965: { $flatten\i2c_target.$procmux$1071_CMP $auto$opt_reduce.cc:137:opt_pmux$1180 $flatten\i2c_target.$procmux$1015_CMP } I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 3 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.12. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 1 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 6 unused cells and 13 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.15. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.16. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.19. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.20. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.22. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.10.23. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11. Executing FSM pass (extract and optimize FSM). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). I: glasgow.hardware.build_plan: build: Not marking top.fx2_crossbar.fsm_state as FSM state register: I: glasgow.hardware.build_plan: build: Register has an initialization value. I: glasgow.hardware.build_plan: build: Not marking top.i2c_target.fsm_state as FSM state register: I: glasgow.hardware.build_plan: build: Register has an initialization value. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\in_fifo_0.\inner.$78 ($dff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$441_Y, Q = \in_fifo_0.inner.r_rdy, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1181 ($sdff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$441_Y, Q = \in_fifo_0.inner.r_rdy). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\in_fifo_0.\inner.$76 ($dff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$449_Y, Q = \in_fifo_0.inner.inner_level, rval = 9'000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1189 ($sdff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$449_Y, Q = \in_fifo_0.inner.inner_level). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\in_fifo_0.\inner.$74 ($dff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$455_Y, Q = \in_fifo_0.inner.r_port__addr, rval = 9'000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1197 ($sdff) from module top (D = $flatten\in_fifo_0.\inner.$12 [8:0], Q = \in_fifo_0.inner.r_port__addr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\in_fifo_0.\inner.$72 ($dff) from module top (D = $flatten\in_fifo_0.\inner.$procmux$461_Y, Q = \in_fifo_0.inner.w_port__addr, rval = 9'000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1203 ($sdff) from module top (D = $flatten\in_fifo_0.\inner.$6 [8:0], Q = \in_fifo_0.inner.w_port__addr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.\bus.$24 ($dff) from module top (D = \i2c_target.bus.U$3.stage1, Q = \i2c_target.bus.sda_r, rval = 1'1). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.\bus.$22 ($dff) from module top (D = \i2c_target.bus.U$2.stage1, Q = \i2c_target.bus.scl_r, rval = 1'1). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$86 ($dff) from module top (D = $flatten\i2c_target.$procmux$806_Y, Q = \i2c_target.scl_o, rval = 1'1). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1211 ($sdff) from module top (D = $flatten\i2c_target.$procmux$806_Y, Q = \i2c_target.scl_o). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$84 ($dff) from module top (D = $flatten\i2c_target.$procmux$819_Y, Q = \i2c_target.write, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1229 ($sdff) from module top (D = $flatten\i2c_target.$procmux$819_Y, Q = \i2c_target.write). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$82 ($dff) from module top (D = $flatten\i2c_target.$procmux$844_Y, Q = \i2c_target.data_i, rval = 8'00000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1245 ($sdff) from module top (D = \i2c_target.shreg_i, Q = \i2c_target.data_i). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$80 ($dff) from module top (D = $flatten\i2c_target.$procmux$858_Y, Q = \i2c_target.shreg_o, rval = 8'00000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1255 ($sdff) from module top (D = $flatten\i2c_target.$procmux$858_Y, Q = \i2c_target.shreg_o). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$78 ($dff) from module top (D = $flatten\i2c_target.$procmux$888_Y, Q = \i2c_target.sda_o, rval = 1'1). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1289 ($sdff) from module top (D = $flatten\i2c_target.$procmux$888_Y, Q = \i2c_target.sda_o). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$76 ($dff) from module top (D = $flatten\i2c_target.$procmux$946_Y, Q = \i2c_target.shreg_i, rval = 8'00000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1341 ($sdff) from module top (D = $flatten\i2c_target.$2 [7:0], Q = \i2c_target.shreg_i). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$74 ($dff) from module top (D = $flatten\i2c_target.$procmux$965_Y, Q = \i2c_target.bitno, rval = 3'000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1349 ($sdff) from module top (D = $flatten\i2c_target.$procmux$965_Y, Q = \i2c_target.bitno). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_target.$72 ($dff) from module top (D = $flatten\i2c_target.$procmux$1003_Y, Q = \i2c_target.fsm_state, rval = 4'0000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1375 ($sdff) from module top (D = $flatten\i2c_target.$procmux$1003_Y, Q = \i2c_target.fsm_state). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_registers.$25 ($dff) from module top (D = $flatten\i2c_registers.$procmux$654_Y, Q = \i2c_registers.$signal, rval = 4'1111). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1415 ($sdff) from module top (D = \i2c_registers.data_o [3:0], Q = \i2c_registers.$signal). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_registers.$21 ($dff) from module top (D = $flatten\i2c_registers.$procmux$669_Y, Q = \i2c_registers.data_o, rval = 8'00000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1419 ($sdff) from module top (D = $flatten\i2c_registers.$procmux$667_Y, Q = \i2c_registers.data_o). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_registers.$19 ($dff) from module top (D = $flatten\i2c_registers.$procmux$677_Y, Q = \i2c_registers.reg_addr, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1425 ($sdff) from module top (D = \i2c_target.data_i [0], Q = \i2c_registers.reg_addr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_registers.$17 ($dff) from module top (D = $flatten\i2c_registers.$procmux$686_Y, Q = \i2c_registers.reg_update, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\i2c_registers.$15 ($dff) from module top (D = $flatten\i2c_registers.$procmux$690_Y, Q = \i2c_registers.latch_addr, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1430 ($sdff) from module top (D = 1'1, Q = \i2c_registers.latch_addr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.\in_fifo_0.$14 ($dff) from module top (D = $flatten\fx2_crossbar.\in_fifo_0.$procmux$505_Y, Q = \fx2_crossbar.in_fifo_0.pending$9, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1436 ($sdff) from module top (D = $flatten\fx2_crossbar.\in_fifo_0.$procmux$505_Y, Q = \fx2_crossbar.in_fifo_0.pending$9). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.\in_fifo_0.$12 ($dff) from module top (D = $flatten\fx2_crossbar.\in_fifo_0.$procmux$511_Y, Q = \fx2_crossbar.in_fifo_0.queued, rval = 10'0000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1448 ($sdff) from module top (D = $flatten\fx2_crossbar.\in_fifo_0.$3 [9:0], Q = \fx2_crossbar.in_fifo_0.queued). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.\bus.$49 ($dff) from module top (D = $flatten\fx2_crossbar.\bus.$1, Q = \fx2_crossbar.bus.nrdy_o, rval = 4'0000). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.\bus.$47 ($dff) from module top (D = \fx2_crossbar.bus.nrdy_i, Q = \fx2_crossbar.bus.nrdy_r, rval = 4'0000). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.$106 ($dff) from module top (D = $flatten\fx2_crossbar.$procmux$534_Y, Q = \fx2_crossbar.fsm_state, rval = 3'000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1456 ($sdff) from module top (D = $flatten\fx2_crossbar.$procmux$534_Y, Q = \fx2_crossbar.fsm_state). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.$104 ($dff) from module top (D = $flatten\fx2_crossbar.$procmux$552_Y, Q = \fx2_crossbar.addr, rval = 2'00). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1466 ($sdff) from module top (D = $flatten\fx2_crossbar.$auto$proc_rom.cc:154:do_switch$381, Q = \fx2_crossbar.addr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.$102 ($dff) from module top (D = $flatten\fx2_crossbar.$procmux$558_Y, Q = \fx2_crossbar.data__oe, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1468 ($sdff) from module top (D = $flatten\fx2_crossbar.$procmux$558_Y, Q = \fx2_crossbar.data__oe). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\fx2_crossbar.$100 ($dff) from module top (D = $flatten\fx2_crossbar.$procmux$566_Y, Q = \fx2_crossbar.sloe, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1476 ($sdff) from module top (D = $flatten\fx2_crossbar.$procmux$566_Y, Q = \fx2_crossbar.sloe). I: glasgow.hardware.build_plan: build: Adding EN signal on $flatten\cd_sync.$9 ($dff) from module top (D = 1'1, Q = \cd_sync.ready). I: glasgow.hardware.build_plan: build: Adding EN signal on $flatten\cd_sync.$11 ($dff) from module top (D = $flatten\cd_sync.$2 [9:0], Q = \cd_sync.timer). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$54 ($dff) from module top (D = $flatten\U$18.$procmux$398_Y, Q = \U$18.src, rval = 5'00000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1486 ($sdff) from module top (D = $flatten\U$18.$procmux$396_Y, Q = \U$18.src). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$52 ($dff) from module top (D = $flatten\U$18.$procmux$406_Y, Q = \U$18.srb, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1492 ($sdff) from module top (D = $flatten\U$18.$procmux$404_Y, Q = \U$18.srb). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$50 ($dff) from module top (D = $flatten\U$18.$procmux$413_Y, Q = \U$18.sr, rval = 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1498 ($sdff) from module top (D = $flatten\U$18.$procmux$411_Y, Q = \U$18.sr). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$48 ($dff) from module top (D = $flatten\U$18.$procmux$417_Y, Q = \U$18.lrp, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding EN signal on $auto$ff.cc:266:slice$1500 ($sdff) from module top (D = \U$18.lr2, Q = \U$18.lrp). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$40 ($dff) from module top (D = \U$18.lr1, Q = \U$18.lr2, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$38 ($dff) from module top (D = \U$18.lr0, Q = \U$18.lr1, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$36 ($dff) from module top (D = \U$18.i$7, Q = \U$18.lr0, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$34 ($dff) from module top (D = \U$18.clk1, Q = \U$18.clk2, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$32 ($dff) from module top (D = \U$18.clk0, Q = \U$18.clk1, rval = 1'0). I: glasgow.hardware.build_plan: build: Adding SRST signal on $flatten\U$18.$30 ($dff) from module top (D = \U$18.clk_buffer.io.i, Q = \U$18.clk0, rval = 1'0). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 73 unused cells and 73 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.12. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 45 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 45 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.15. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.19. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.22. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.12.23. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.13. Executing WREDUCE pass (reducing word size of cells). I: glasgow.hardware.build_plan: build: Removed top 26 address bits (of 32) from memory init port top.$flatten\fx2_crossbar.$auto$mem.cc:328:emit$384 ($flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382). I: glasgow.hardware.build_plan: build: Removed top 2 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1066_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 2 bits (of 4) from mux cell top.$flatten\i2c_target.$procmux$1054 ($mux). I: glasgow.hardware.build_plan: build: Removed top 2 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1052_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1039_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1028_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1021_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from mux cell top.$flatten\i2c_target.$procmux$1017 ($mux). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1015_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from mux cell top.$flatten\i2c_target.$procmux$993 ($mux). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1461 ($ne). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1473 ($ne). I: glasgow.hardware.build_plan: build: Removed top 3 bits (of 4) from port B of cell top.$flatten\i2c_target.$procmux$1071_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port Y of cell top.$flatten\i2c_target.$42 ($add). I: glasgow.hardware.build_plan: build: Removed top 8 bits (of 9) from port B of cell top.$flatten\i2c_target.$41 ($or). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 9) from port Y of cell top.$flatten\i2c_target.$41 ($or). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 9) from port A of cell top.$flatten\i2c_target.$41 ($or). I: glasgow.hardware.build_plan: build: Removed top 7 bits (of 8) from port B of cell top.$flatten\i2c_registers.$procmux$704_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1266 ($ne). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1234 ($ne). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1298 ($ne). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 11) from port Y of cell top.$flatten\fx2_crossbar.\in_fifo_0.$10 ($add). I: glasgow.hardware.build_plan: build: Removed top 2 bits (of 3) from port B of cell top.$flatten\fx2_crossbar.$procmux$545_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 3) from port B of cell top.$flatten\fx2_crossbar.$procmux$544_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 3) from port B of cell top.$flatten\fx2_crossbar.$procmux$540_CMP0 ($eq). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1394 ($ne). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from port A of cell top.$flatten\fx2_crossbar.$53 ($and). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from mux cell top.$flatten\in_fifo_0.\inner.$44 ($mux). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from mux cell top.$flatten\in_fifo_0.\inner.$50 ($mux). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from port Y of cell top.$flatten\in_fifo_0.\inner.$57 ($add). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from port Y of cell top.$flatten\in_fifo_0.\inner.$64 ($sub). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 6) from port Y of cell top.$flatten\U$18.$25 ($sub). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 129) from port Y of cell top.$flatten\U$18.$23 ($add). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 11) from port Y of cell top.$flatten\cd_sync.$7 ($add). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from port Y of cell top.$flatten\in_fifo_0.\inner.$43 ($add). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from port Y of cell top.$flatten\in_fifo_0.\inner.$49 ($add). I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 129) from wire top.$flatten\U$18.$3. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 11) from wire top.$flatten\cd_sync.$2. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 11) from wire top.$flatten\fx2_crossbar.\in_fifo_0.$3. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from wire top.$flatten\i2c_target.$16. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 9) from wire top.$flatten\i2c_target.$2. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from wire top.$flatten\i2c_target.$procmux$1017_Y. I: glasgow.hardware.build_plan: build: Removed top 2 bits (of 4) from wire top.$flatten\i2c_target.$procmux$1054_Y. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 4) from wire top.$flatten\i2c_target.$procmux$993_Y. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from wire top.$flatten\in_fifo_0.\inner.$11. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from wire top.$flatten\in_fifo_0.\inner.$12. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from wire top.$flatten\in_fifo_0.\inner.$19. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from wire top.$flatten\in_fifo_0.\inner.$26. I: glasgow.hardware.build_plan: build: Removed top 1 bits (of 10) from wire top.$flatten\in_fifo_0.\inner.$5. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.14. Executing PEEPOPT pass (run peephole optimizers). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 13 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.16. Executing SHARE pass (SAT-based resource sharing). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.17. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.17.1. Executing Verilog-2005 frontend: /share/cmp2lut.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/cmp2lut.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lut_cmp_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.17.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.18. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.20. Executing ALUMACC pass (create $alu and $macc cells). I: glasgow.hardware.build_plan: build: Extracting $alu and $macc cells in module top: I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\U$18.$23 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\U$18.$25 ($sub). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\cd_sync.$7 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\fx2_crossbar.\in_fifo_0.$10 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\i2c_target.$42 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\in_fifo_0.\inner.$43 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\in_fifo_0.\inner.$49 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\in_fifo_0.\inner.$57 ($add). I: glasgow.hardware.build_plan: build: creating $macc model for $flatten\in_fifo_0.\inner.$64 ($sub). I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\in_fifo_0.\inner.$64. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\in_fifo_0.\inner.$57. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\in_fifo_0.\inner.$49. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\in_fifo_0.\inner.$43. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\i2c_target.$42. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\fx2_crossbar.\in_fifo_0.$10. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\cd_sync.$7. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\U$18.$25. I: glasgow.hardware.build_plan: build: creating $alu model for $macc $flatten\U$18.$23. I: glasgow.hardware.build_plan: build: creating $alu model for $flatten\fx2_crossbar.\in_fifo_0.$6 ($ge): new $alu I: glasgow.hardware.build_plan: build: creating $alu model for $flatten\fx2_crossbar.\in_fifo_0.$9 ($lt): merged with $flatten\fx2_crossbar.\in_fifo_0.$6. I: glasgow.hardware.build_plan: build: creating $alu model for $flatten\i2c_registers.$10 ($lt): new $alu I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\i2c_registers.$10: $auto$alumacc.cc:495:replace_alu$1524 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\fx2_crossbar.\in_fifo_0.$6, $flatten\fx2_crossbar.\in_fifo_0.$9: $auto$alumacc.cc:495:replace_alu$1529 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\U$18.$23: $auto$alumacc.cc:495:replace_alu$1542 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\U$18.$25: $auto$alumacc.cc:495:replace_alu$1545 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\cd_sync.$7: $auto$alumacc.cc:495:replace_alu$1548 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\fx2_crossbar.\in_fifo_0.$10: $auto$alumacc.cc:495:replace_alu$1551 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\i2c_target.$42: $auto$alumacc.cc:495:replace_alu$1554 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\in_fifo_0.\inner.$43: $auto$alumacc.cc:495:replace_alu$1557 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\in_fifo_0.\inner.$49: $auto$alumacc.cc:495:replace_alu$1560 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\in_fifo_0.\inner.$57: $auto$alumacc.cc:495:replace_alu$1563 I: glasgow.hardware.build_plan: build: creating $alu cell for $flatten\in_fifo_0.\inner.$64: $auto$alumacc.cc:495:replace_alu$1566 I: glasgow.hardware.build_plan: build: created 11 $alu and 0 $macc cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 1 unused cells and 4 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.9. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.12. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.13. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.15. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.21.16. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22. Executing MEMORY pass. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.1. Executing OPT_MEM pass (optimize memories). I: glasgow.hardware.build_plan: build: Performed a total of 0 transformations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). I: glasgow.hardware.build_plan: build: Performed a total of 0 transformations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). I: glasgow.hardware.build_plan: build: Checking read port `$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382'[0] in module `\top': merging output FF to cell. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 1 unused cells and 3 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). I: glasgow.hardware.build_plan: build: Performed a total of 0 transformations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). I: glasgow.hardware.build_plan: build: using FF mapping for memory top.$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382 I: glasgow.hardware.build_plan: build: mapping memory top.in_fifo_0.inner.storage via $__ICE40_RAM4K_ I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.25. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.25.1. Executing Verilog-2005 frontend: /share/ice40/brams_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/brams_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__ICE40_RAM4K_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.25.2. Executing Verilog-2005 frontend: /share/ice40/spram_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/spram_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__ICE40_SPRAM_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.25.3. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using template $paramod$dd3348ae87356301b9facf18ec8783aacc96eb8d\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.26. Executing ICE40_BRAMINIT pass. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 1 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$1212 ($sdffe) from module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 8 unused cells and 127 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.5. Rerunning OPT passes. (Removed registers in this run.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.6. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.7. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.8. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 3 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.27.10. Finished fast OPT passes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). I: glasgow.hardware.build_plan: build: Mapping memory $flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382 in module \top: I: glasgow.hardware.build_plan: build: created 64 $dff cells and 0 static cells of width 2. I: glasgow.hardware.build_plan: build: Extracted data FF from read port 0 of top.$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382: $$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdreg[0] I: glasgow.hardware.build_plan: build: read interface: 1 $dff and 63 $mux cells. I: glasgow.hardware.build_plan: build: write interface: 0 write mux blocks. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: dead port 1/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][1]$1682. I: glasgow.hardware.build_plan: build: dead port 2/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][1]$1682. I: glasgow.hardware.build_plan: build: dead port 1/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][3]$1688. I: glasgow.hardware.build_plan: build: dead port 2/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][3]$1688. I: glasgow.hardware.build_plan: build: dead port 1/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][5]$1694. I: glasgow.hardware.build_plan: build: dead port 2/2 on $mux $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][5]$1694. I: glasgow.hardware.build_plan: build: Removed 6 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][4]$1691: I: glasgow.hardware.build_plan: build: Old ports: A=2'11, B=2'10, Y=$memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][2]$a$1674 I: glasgow.hardware.build_plan: build: New ports: A=1'1, B=1'0, Y=$memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][2]$a$1674 [0] I: glasgow.hardware.build_plan: build: New connections: $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][2]$a$1674 [1] = 1'1 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][3][6]$1697: I: glasgow.hardware.build_plan: build: Old ports: A=2'00, B=2'10, Y=$memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][3]$a$1677 I: glasgow.hardware.build_plan: build: New ports: A=1'0, B=1'1, Y=$memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][3]$a$1677 [1] I: glasgow.hardware.build_plan: build: New connections: $memory$flatten\fx2_crossbar.$auto$proc_rom.cc:155:do_switch$382$rdmux[0][2][3]$a$1677 [0] = 1'0 I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\fx2_crossbar.$procmux$534: { $flatten\fx2_crossbar.$procmux$545_CMP $flatten\fx2_crossbar.$procmux$544_CMP $auto$opt_reduce.cc:137:opt_pmux$1848 } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\fx2_crossbar.$procmux$542: I: glasgow.hardware.build_plan: build: Old ports: A=3'100, B=3'011, Y=$flatten\fx2_crossbar.$procmux$542_Y I: glasgow.hardware.build_plan: build: New ports: A=2'10, B=2'01, Y={ $flatten\fx2_crossbar.$procmux$542_Y [2] $flatten\fx2_crossbar.$procmux$542_Y [0] } I: glasgow.hardware.build_plan: build: New connections: $flatten\fx2_crossbar.$procmux$542_Y [1] = $flatten\fx2_crossbar.$procmux$542_Y [0] I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\fx2_crossbar.$procmux$595: I: glasgow.hardware.build_plan: build: Old ports: A=4'0000, B={ $flatten\fx2_crossbar.$6 2'00 }, Y=\fx2_crossbar.bus.nrdy_i I: glasgow.hardware.build_plan: build: New ports: A=2'00, B=$flatten\fx2_crossbar.$6, Y=\fx2_crossbar.bus.nrdy_i [3:2] I: glasgow.hardware.build_plan: build: New connections: \fx2_crossbar.bus.nrdy_i [1:0] = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $pmux cell $flatten\i2c_registers.$procmux$703: I: glasgow.hardware.build_plan: build: Old ports: A=8'00000000, B={ 12'101001010000 \i2c_registers.$signal }, Y=$flatten\i2c_registers.$2 I: glasgow.hardware.build_plan: build: New ports: A=5'00000, B={ 6'101010 \i2c_registers.$signal }, Y={ $flatten\i2c_registers.$2 [5] $flatten\i2c_registers.$2 [3:0] } I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_registers.$2 [7:6] $flatten\i2c_registers.$2 [4] } = { $flatten\i2c_registers.$2 [5] 2'00 } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1011: I: glasgow.hardware.build_plan: build: Old ports: A=4'1000, B=4'0001, Y=$flatten\i2c_target.$procmux$1011_Y I: glasgow.hardware.build_plan: build: New ports: A=2'10, B=2'01, Y={ $flatten\i2c_target.$procmux$1011_Y [3] $flatten\i2c_target.$procmux$1011_Y [0] } I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1011_Y [2:1] = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1017: I: glasgow.hardware.build_plan: build: Old ports: A=3'111, B=3'001, Y=$auto$wreduce.cc:514:run$1513 [2:0] I: glasgow.hardware.build_plan: build: New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:514:run$1513 [1] I: glasgow.hardware.build_plan: build: New connections: { $auto$wreduce.cc:514:run$1513 [2] $auto$wreduce.cc:514:run$1513 [0] } = { $auto$wreduce.cc:514:run$1513 [1] 1'1 } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1019: I: glasgow.hardware.build_plan: build: Old ports: A={ 1'0 $auto$wreduce.cc:514:run$1513 [2:0] }, B=4'0000, Y=$flatten\i2c_target.$procmux$1019_Y I: glasgow.hardware.build_plan: build: New ports: A=$auto$wreduce.cc:514:run$1513 [2:0], B=3'000, Y=$flatten\i2c_target.$procmux$1019_Y [2:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1019_Y [3] = 1'0 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1024: I: glasgow.hardware.build_plan: build: Old ports: A=4'0100, B=4'0001, Y=$flatten\i2c_target.$procmux$1024_Y I: glasgow.hardware.build_plan: build: New ports: A=2'10, B=2'01, Y={ $flatten\i2c_target.$procmux$1024_Y [2] $flatten\i2c_target.$procmux$1024_Y [0] } I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_target.$procmux$1024_Y [3] $flatten\i2c_target.$procmux$1024_Y [1] } = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1035: I: glasgow.hardware.build_plan: build: Old ports: A=4'0110, B=4'0001, Y=$flatten\i2c_target.$procmux$1035_Y I: glasgow.hardware.build_plan: build: New ports: A=2'10, B=2'01, Y=$flatten\i2c_target.$procmux$1035_Y [1:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1035_Y [3:2] = { 1'0 $flatten\i2c_target.$procmux$1035_Y [1] } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1046: I: glasgow.hardware.build_plan: build: Old ports: A=4'0101, B=4'0100, Y=$flatten\i2c_target.$procmux$1046_Y I: glasgow.hardware.build_plan: build: New ports: A=1'1, B=1'0, Y=$flatten\i2c_target.$procmux$1046_Y [0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1046_Y [3:1] = 3'010 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1054: I: glasgow.hardware.build_plan: build: Old ports: A=2'00, B=2'11, Y=$auto$wreduce.cc:514:run$1514 [1:0] I: glasgow.hardware.build_plan: build: New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:514:run$1514 [0] I: glasgow.hardware.build_plan: build: New connections: $auto$wreduce.cc:514:run$1514 [1] = $auto$wreduce.cc:514:run$1514 [0] I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1062: I: glasgow.hardware.build_plan: build: Old ports: A={ 2'00 $auto$wreduce.cc:514:run$1514 [1:0] }, B=4'0001, Y=$flatten\i2c_target.$procmux$1062_Y I: glasgow.hardware.build_plan: build: New ports: A=$auto$wreduce.cc:514:run$1514 [1:0], B=2'01, Y=$flatten\i2c_target.$procmux$1062_Y [1:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1062_Y [3:2] = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1069: I: glasgow.hardware.build_plan: build: Old ports: A=4'0010, B=4'0000, Y=$flatten\i2c_target.$procmux$1069_Y I: glasgow.hardware.build_plan: build: New ports: A=1'1, B=1'0, Y=$flatten\i2c_target.$procmux$1069_Y [1] I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_target.$procmux$1069_Y [3:2] $flatten\i2c_target.$procmux$1069_Y [0] } = 3'000 I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$858: $flatten\i2c_target.$procmux$1015_CMP I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$888: { $flatten\i2c_target.$procmux$1028_CMP $auto$opt_reduce.cc:137:opt_pmux$1852 $auto$opt_reduce.cc:137:opt_pmux$1850 } I: glasgow.hardware.build_plan: build: New ctrl vector for $pmux cell $flatten\i2c_target.$procmux$965: $auto$opt_reduce.cc:137:opt_pmux$1854 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$993: I: glasgow.hardware.build_plan: build: Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:514:run$1515 [2:0] I: glasgow.hardware.build_plan: build: New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:514:run$1515 [0] I: glasgow.hardware.build_plan: build: New connections: $auto$wreduce.cc:514:run$1515 [2:1] = { $auto$wreduce.cc:514:run$1515 [0] 1'0 } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$999: I: glasgow.hardware.build_plan: build: Old ports: A={ 1'0 $auto$wreduce.cc:514:run$1515 [2:0] }, B=4'0001, Y=$flatten\i2c_target.$procmux$999_Y I: glasgow.hardware.build_plan: build: New ports: A=$auto$wreduce.cc:514:run$1515 [2:0], B=3'001, Y=$flatten\i2c_target.$procmux$999_Y [2:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$999_Y [3] = 1'0 I: glasgow.hardware.build_plan: build: New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$1853: { $flatten\i2c_target.$procmux$1015_CMP $flatten\i2c_target.$procmux$1039_CMP $flatten\i2c_target.$procmux$1066_CMP } I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1001: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$999_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1001_Y I: glasgow.hardware.build_plan: build: New ports: A=$flatten\i2c_target.$procmux$999_Y [2:0], B=3'000, Y=$flatten\i2c_target.$procmux$1001_Y [2:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1001_Y [3] = 1'0 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1013: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1011_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1013_Y I: glasgow.hardware.build_plan: build: New ports: A={ $flatten\i2c_target.$procmux$1011_Y [3] $flatten\i2c_target.$procmux$1011_Y [0] }, B=2'00, Y={ $flatten\i2c_target.$procmux$1013_Y [3] $flatten\i2c_target.$procmux$1013_Y [0] } I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1013_Y [2:1] = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1019: I: glasgow.hardware.build_plan: build: Old ports: A=$auto$wreduce.cc:514:run$1513 [2:0], B=3'000, Y=$flatten\i2c_target.$procmux$1019_Y [2:0] I: glasgow.hardware.build_plan: build: New ports: A={ $auto$wreduce.cc:514:run$1513 [1] 1'1 }, B=2'00, Y=$flatten\i2c_target.$procmux$1019_Y [1:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1019_Y [2] = $flatten\i2c_target.$procmux$1019_Y [1] I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1026: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1024_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1026_Y I: glasgow.hardware.build_plan: build: New ports: A={ $flatten\i2c_target.$procmux$1024_Y [2] $flatten\i2c_target.$procmux$1024_Y [0] }, B=2'00, Y={ $flatten\i2c_target.$procmux$1026_Y [2] $flatten\i2c_target.$procmux$1026_Y [0] } I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_target.$procmux$1026_Y [3] $flatten\i2c_target.$procmux$1026_Y [1] } = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1037: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1035_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1037_Y I: glasgow.hardware.build_plan: build: New ports: A=$flatten\i2c_target.$procmux$1035_Y [1:0], B=2'00, Y=$flatten\i2c_target.$procmux$1037_Y [1:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1037_Y [3:2] = { 1'0 $flatten\i2c_target.$procmux$1037_Y [1] } I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1048: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1046_Y, B=4'0001, Y=$flatten\i2c_target.$procmux$1048_Y I: glasgow.hardware.build_plan: build: New ports: A={ 1'1 $flatten\i2c_target.$procmux$1046_Y [0] }, B=2'01, Y={ $flatten\i2c_target.$procmux$1048_Y [2] $flatten\i2c_target.$procmux$1048_Y [0] } I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_target.$procmux$1048_Y [3] $flatten\i2c_target.$procmux$1048_Y [1] } = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1064: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1062_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1064_Y I: glasgow.hardware.build_plan: build: New ports: A=$flatten\i2c_target.$procmux$1062_Y [1:0], B=2'00, Y=$flatten\i2c_target.$procmux$1064_Y [1:0] I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1064_Y [3:2] = 2'00 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$999: I: glasgow.hardware.build_plan: build: Old ports: A=$auto$wreduce.cc:514:run$1515 [2:0], B=3'001, Y=$flatten\i2c_target.$procmux$999_Y [2:0] I: glasgow.hardware.build_plan: build: New ports: A={ $auto$wreduce.cc:514:run$1515 [0] $auto$wreduce.cc:514:run$1515 [0] }, B=2'01, Y={ $flatten\i2c_target.$procmux$999_Y [2] $flatten\i2c_target.$procmux$999_Y [0] } I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$999_Y [1] = 1'0 I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1001: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$999_Y [2:0], B=3'000, Y=$flatten\i2c_target.$procmux$1001_Y [2:0] I: glasgow.hardware.build_plan: build: New ports: A={ $flatten\i2c_target.$procmux$999_Y [2] $flatten\i2c_target.$procmux$999_Y [0] }, B=2'00, Y={ $flatten\i2c_target.$procmux$1001_Y [2] $flatten\i2c_target.$procmux$1001_Y [0] } I: glasgow.hardware.build_plan: build: New connections: $flatten\i2c_target.$procmux$1001_Y [1] = 1'0 I: glasgow.hardware.build_plan: build: Consolidated identical input bits for $mux cell $flatten\i2c_target.$procmux$1050: I: glasgow.hardware.build_plan: build: Old ports: A=$flatten\i2c_target.$procmux$1048_Y, B=4'0000, Y=$flatten\i2c_target.$procmux$1050_Y I: glasgow.hardware.build_plan: build: New ports: A={ $flatten\i2c_target.$procmux$1048_Y [2] $flatten\i2c_target.$procmux$1048_Y [0] }, B=2'00, Y={ $flatten\i2c_target.$procmux$1050_Y [2] $flatten\i2c_target.$procmux$1050_Y [0] } I: glasgow.hardware.build_plan: build: New connections: { $flatten\i2c_target.$procmux$1050_Y [3] $flatten\i2c_target.$procmux$1050_Y [1] } = 2'00 I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 31 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 5 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 1 unused cells and 127 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.9. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.12. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.13. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1455 ($sdff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1455 ($sdff) from module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 2 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.15. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.16. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.19. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.20. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$1454 ($sdff) from module top. I: glasgow.hardware.build_plan: build: Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$1454 ($sdff) from module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.22. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.23. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.26. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.27. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 2 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.29. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.30. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Evaluating internal representation of mux trees. I: glasgow.hardware.build_plan: build: Analyzing evaluation results. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.33. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.34. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.36. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.29.37. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.31. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.31.1. Executing Verilog-2005 frontend: /share/techmap.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/techmap.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_bool_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_logic_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_compare_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_various'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_registers'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_shiftx'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_fa'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lcu_brent_kung'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alu'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_macc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alumacc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_u'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_trunc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_div'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_mod'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_floor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_divfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_modfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pow'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pmux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_demux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lut'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.31.2. Executing Verilog-2005 frontend: /share/ice40/arith_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/arith_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_80_ice40_alu'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.31.3. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $mux. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $dff. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $ne. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $or. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $sdffe. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $reduce_and. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $reduce_bool. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $reduce_or. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $not. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $and. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $sdff. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $eq. I: glasgow.hardware.build_plan: build: Using template $paramod$b6ec48645094baeb70d6b93add0cdbbe7498ad3c\_90_pmux for cells of type $pmux. I: glasgow.hardware.build_plan: build: Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. I: glasgow.hardware.build_plan: build: Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $logic_not. I: glasgow.hardware.build_plan: build: Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$70d30c21ff772b34d0d1da2801fbd781dc3c70e4\_90_pmux for cells of type $pmux. I: glasgow.hardware.build_plan: build: Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$10ed987432f06055e5279101f9ec60a49861b43c\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$2fff7390d0c2bf21f9d4a24170e0e0160f5d0249\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $dffe. I: glasgow.hardware.build_plan: build: Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. I: glasgow.hardware.build_plan: build: Using template $paramod$constmap:7e7b0a15aaca16161841ffdeb0270bfb1257cf5d$paramod$640153b3f54eea4944e561520acd295aeb1e03d2\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. I: glasgow.hardware.build_plan: build: Using template $paramod$6f67705c43e5e94c02b6ebb52209ce5aa5ade4c1\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$754650b284649a026620fc6856e5b6886cbfe794\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ice40_alu for cells of type $alu. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $xor. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $pos. I: glasgow.hardware.build_plan: build: Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 203 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 155 unused cells and 665 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.32.5. Finished fast OPT passes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33. Executing ICE40_OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.1. Running ICE40 specific optimizations. I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1524.slice[0].carry: CO=\i2c_target.data_i [1] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1542.slice[0].carry: CO=\U$18.sr [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1545.slice[0].carry: CO=\U$18.src [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1548.slice[0].carry: CO=\cd_sync.timer [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1551.slice[0].carry: CO=\fx2_crossbar.in_fifo_0.queued [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1554.slice[0].carry: CO=\i2c_target.bitno [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1557.slice[0].carry: CO=\in_fifo_0.inner.w_port__addr [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1560.slice[0].carry: CO=\in_fifo_0.inner.r_port__addr [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1563.slice[0].carry: CO=\in_fifo_0.inner.inner_level [0] I: glasgow.hardware.build_plan: build: Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:495:replace_alu$1566.slice[0].carry: CO=\in_fifo_0.inner.inner_level [0] I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.2. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.3. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 1 unused cells and 0 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.6. Rerunning OPT passes. (Removed registers in this run.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.7. Running ICE40 specific optimizations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.9. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.10. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.33.12. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.35. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.35.1. Executing Verilog-2005 frontend: /share/ice40/ff_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/ff_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_N_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_NP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_NP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_PP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_PP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_NP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_NP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_PP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_PP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.35.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. I: glasgow.hardware.build_plan: build: Using template \$_DFF_P_ for cells of type $_DFF_P_. I: glasgow.hardware.build_plan: build: Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. I: glasgow.hardware.build_plan: build: Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.36. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1542.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1545.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1548.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1551.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1554.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1557.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1560.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1563.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: Mapping top.$auto$alumacc.cc:495:replace_alu$1566.slice[0].carry ($lut). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38. Executing ICE40_OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.1. Running ICE40 specific optimizations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.2. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.3. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 390 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 3 unused cells and 2806 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.6. Rerunning OPT passes. (Removed registers in this run.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.7. Running ICE40 specific optimizations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.9. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.12. Rerunning OPT passes. (Removed registers in this run.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.13. Running ICE40 specific optimizations. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.14. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.15. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.16. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.17. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.38.18. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.39. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.39.1. Executing Verilog-2005 frontend: /share/ice40/latches_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/latches_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DLATCH_N_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DLATCH_P_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.39.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.40. Executing Verilog-2005 frontend: /share/ice40/abc9_model.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/abc9_model.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41. Executing ABC9 pass. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.1. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.2. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.3. Executing SCC pass (detecting logic loops). I: glasgow.hardware.build_plan: build: Found 0 SCCs in module top. I: glasgow.hardware.build_plan: build: Found 0 SCCs. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.4. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.5. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.5.1. Executing Verilog-2005 frontend: /share/techmap.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/techmap.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_bool_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_logic_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_compare_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_various'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_registers'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_shiftx'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_fa'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lcu_brent_kung'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alu'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_macc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alumacc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_u'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_trunc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_div'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_mod'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_floor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_divfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_modfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pow'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pmux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_demux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lut'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.5.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.6.9. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.7. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.7.1. Executing Verilog-2005 frontend: /share/abc9_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/abc9_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.7.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.8. Executing Verilog-2005 frontend: /share/abc9_model.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/abc9_model.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `$__ABC9_DELAY'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.9. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.10. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.11. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.12. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.12.1. Executing Verilog-2005 frontend: /share/techmap.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/techmap.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_bool_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_logic_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_compare_ops'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_various'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_simplemap_registers'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_shift_shiftx'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_fa'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lcu_brent_kung'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alu'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_macc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_alumacc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_u'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_trunc'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_div'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_mod'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__div_mod_floor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_divfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_modfloor'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pow'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_pmux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_demux'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\_90_lut'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.12.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. I: glasgow.hardware.build_plan: build: Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4. I: glasgow.hardware.build_plan: build: Using template SB_CARRY for cells of type SB_CARRY. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $logic_or. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $logic_and. I: glasgow.hardware.build_plan: build: Using extmapper simplemap for cells of type $mux. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13. Executing OPT pass (performing simple optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.1. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.2. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed a total of 12 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: No muxes found in this module. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.5. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.6. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 24 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.8. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.9. Rerunning OPT passes. (Maybe there is more to do..) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). I: glasgow.hardware.build_plan: build: Running muxtree optimizer on module \top.. I: glasgow.hardware.build_plan: build: Creating internal representation of mux trees. I: glasgow.hardware.build_plan: build: No muxes found in this module. I: glasgow.hardware.build_plan: build: Removed 0 multiplexer ports. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). I: glasgow.hardware.build_plan: build: Optimizing cells in module \top. I: glasgow.hardware.build_plan: build: Performed a total of 0 changes. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.12. Executing OPT_MERGE pass (detect identical cells). I: glasgow.hardware.build_plan: build: Finding identical cells in module `\top'. I: glasgow.hardware.build_plan: build: Removed a total of 0 cells. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.13. Executing OPT_DFF pass (perform DFF optimizations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). I: glasgow.hardware.build_plan: build: Finding unused cells or wires in module \top.. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.15. Executing OPT_EXPR pass (perform const folding). I: glasgow.hardware.build_plan: build: Optimizing module top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.13.16. Finished OPT passes. (There is nothing left to do.) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.14. Executing AIGMAP pass (map logic to AIG). I: glasgow.hardware.build_plan: build: Module top: replaced 7 cells with 43 new cells, skipped 11 cells. I: glasgow.hardware.build_plan: build: replaced 2 cell types: I: glasgow.hardware.build_plan: build: 2 $_OR_ I: glasgow.hardware.build_plan: build: 5 $_MUX_ I: glasgow.hardware.build_plan: build: not replaced 3 cell types: I: glasgow.hardware.build_plan: build: 8 $specify2 I: glasgow.hardware.build_plan: build: 1 $_NOT_ I: glasgow.hardware.build_plan: build: 2 $_AND_ I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15. Executing AIGMAP pass (map logic to AIG). I: glasgow.hardware.build_plan: build: Module top: replaced 623 cells with 3518 new cells, skipped 1898 cells. I: glasgow.hardware.build_plan: build: replaced 4 cell types: I: glasgow.hardware.build_plan: build: 265 $_OR_ I: glasgow.hardware.build_plan: build: 9 $_XOR_ I: glasgow.hardware.build_plan: build: 12 $_ORNOT_ I: glasgow.hardware.build_plan: build: 337 $_MUX_ I: glasgow.hardware.build_plan: build: not replaced 19 cell types: I: glasgow.hardware.build_plan: build: 90 $scopeinfo I: glasgow.hardware.build_plan: build: 115 $_NOT_ I: glasgow.hardware.build_plan: build: 185 $_AND_ I: glasgow.hardware.build_plan: build: 59 SB_IO I: glasgow.hardware.build_plan: build: 31 SB_DFF I: glasgow.hardware.build_plan: build: 1 SB_GB_IO I: glasgow.hardware.build_plan: build: 20 SB_DFFE I: glasgow.hardware.build_plan: build: 11 SB_DFFSR I: glasgow.hardware.build_plan: build: 355 SB_DFFESR I: glasgow.hardware.build_plan: build: 1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010 I: glasgow.hardware.build_plan: build: 16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010100001 I: glasgow.hardware.build_plan: build: 2 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011 I: glasgow.hardware.build_plan: build: 11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011100000 I: glasgow.hardware.build_plan: build: 16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100010010 I: glasgow.hardware.build_plan: build: 1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010000101 I: glasgow.hardware.build_plan: build: 417 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101 I: glasgow.hardware.build_plan: build: 377 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011 I: glasgow.hardware.build_plan: build: 1 $paramod$f99246623db89700451daf7d443842de27e23616\SB_RAM40_4K I: glasgow.hardware.build_plan: build: 189 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.1. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.2. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.3. Executing XAIGER backend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Extracted 1500 AND gates and 5881 wires from module `top' to a netlist network with 491 inputs and 951 outputs. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.5. Executing ABC9. I: glasgow.hardware.build_plan: build: Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 I: glasgow.hardware.build_plan: build: ABC: ABC command line: "source /abc.script". I: glasgow.hardware.build_plan: build: ABC: I: glasgow.hardware.build_plan: build: ABC: + read_lut /input.lut I: glasgow.hardware.build_plan: build: ABC: + read_box /input.box I: glasgow.hardware.build_plan: build: ABC: + &read /input.xaig I: glasgow.hardware.build_plan: build: ABC: + &ps I: glasgow.hardware.build_plan: build: ABC: /input : i/o = 491/ 951 and = 1127 lev = 16 (0.90) mem = 0.08 MB box = 1030 bb = 841 I: glasgow.hardware.build_plan: build: ABC: + &scorr I: glasgow.hardware.build_plan: build: ABC: Warning: The network is combinational. I: glasgow.hardware.build_plan: build: ABC: + &sweep I: glasgow.hardware.build_plan: build: ABC: + &dc2 I: glasgow.hardware.build_plan: build: ABC: + &dch -f I: glasgow.hardware.build_plan: build: ABC: + &ps I: glasgow.hardware.build_plan: build: ABC: /input : i/o = 491/ 951 and = 1582 lev = 11 (0.70) mem = 0.09 MB ch = 224 box = 1024 bb = 841 I: glasgow.hardware.build_plan: build: ABC: cst = 0 cls = 217 lit = 224 unused = 2839 proof = 0 I: glasgow.hardware.build_plan: build: ABC: + &if -W 250 -v I: glasgow.hardware.build_plan: build: ABC: K = 4. Memory (bytes): Truth = 0. Cut = 52. Obj = 108. Set = 516. CutMin = no I: glasgow.hardware.build_plan: build: ABC: Node = 1582. Ch = 217. Total mem = 0.66 MB. Peak cut mem = 0.03 MB. I: glasgow.hardware.build_plan: build: ABC: P: Del = 17424.00. Ar = 525.0. Edge = 1702. Cut = 9304. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: P: Del = 17424.00. Ar = 512.0. Edge = 1804. Cut = 8519. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: P: Del = 17424.00. Ar = 481.0. Edge = 1494. Cut = 8830. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: F: Del = 17424.00. Ar = 476.0. Edge = 1482. Cut = 9648. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: A: Del = 17424.00. Ar = 471.0. Edge = 1420. Cut = 9730. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: A: Del = 17424.00. Ar = 470.0. Edge = 1419. Cut = 9722. T = 0.00 sec I: glasgow.hardware.build_plan: build: ABC: Total time = 0.01 sec I: glasgow.hardware.build_plan: build: ABC: + &write -n /output.aig I: glasgow.hardware.build_plan: build: ABC: + &mfs I: glasgow.hardware.build_plan: build: ABC: + &ps -l I: glasgow.hardware.build_plan: build: ABC: /input : i/o = 491/ 951 and = 1108 lev = 13 (0.71) mem = 0.08 MB box = 1024 bb = 841 I: glasgow.hardware.build_plan: build: ABC: Mapping (K=4) : lut = 466 edge = 1398 lev = 7 (0.47) Boxes are not in a topological order. Switching to level computation without boxes. I: glasgow.hardware.build_plan: build: ABC: levB = 13 mem = 0.03 MB I: glasgow.hardware.build_plan: build: ABC: LUT = 466 : 2=75 16.1 % 3=316 67.8 % 4=75 16.1 % Ave = 3.00 I: glasgow.hardware.build_plan: build: ABC: + &write -n /output.aig I: glasgow.hardware.build_plan: build: ABC: + time I: glasgow.hardware.build_plan: build: ABC: elapse: 0.10 seconds, total: 0.10 seconds I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.6. Executing AIGER frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed 1571 unused cells and 5998 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.15.7. Executing ABC9_OPS pass (helper functions for ABC9). I: glasgow.hardware.build_plan: build: ABC RESULTS: $lut cells: 478 I: glasgow.hardware.build_plan: build: ABC RESULTS: $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells: 183 I: glasgow.hardware.build_plan: build: ABC RESULTS: input signals: 59 I: glasgow.hardware.build_plan: build: ABC RESULTS: output signals: 924 I: glasgow.hardware.build_plan: build: Removing temp directory. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.16. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.16.1. Executing Verilog-2005 frontend: /share/abc9_unmap.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/abc9_unmap.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.41.16.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. I: glasgow.hardware.build_plan: build: Using template $paramod$f99246623db89700451daf7d443842de27e23616\SB_RAM40_4K for cells of type $paramod$f99246623db89700451daf7d443842de27e23616\SB_RAM40_4K. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.43. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.43.1. Executing Verilog-2005 frontend: /share/ice40/ff_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/ff_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_N_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_NP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_NP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_PP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFF_PP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_NP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_DFFE_PP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_NP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_NP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_PP0_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFF_PP1_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.43.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed 55 unused cells and 7554 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.44. Executing OPT_LUT pass (optimize LUTs). I: glasgow.hardware.build_plan: build: Discovering LUTs. I: glasgow.hardware.build_plan: build: Number of LUTs: 661 I: glasgow.hardware.build_plan: build: 1-LUT 12 I: glasgow.hardware.build_plan: build: 2-LUT 84 I: glasgow.hardware.build_plan: build: 3-LUT 489 I: glasgow.hardware.build_plan: build: 4-LUT 76 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#0) 173 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#1) 174 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Eliminating LUTs. I: glasgow.hardware.build_plan: build: Number of LUTs: 661 I: glasgow.hardware.build_plan: build: 1-LUT 12 I: glasgow.hardware.build_plan: build: 2-LUT 84 I: glasgow.hardware.build_plan: build: 3-LUT 489 I: glasgow.hardware.build_plan: build: 4-LUT 76 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#0) 173 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#1) 174 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Combining LUTs. I: glasgow.hardware.build_plan: build: Number of LUTs: 637 I: glasgow.hardware.build_plan: build: 1-LUT 12 I: glasgow.hardware.build_plan: build: 2-LUT 57 I: glasgow.hardware.build_plan: build: 3-LUT 471 I: glasgow.hardware.build_plan: build: 4-LUT 97 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#0) 173 I: glasgow.hardware.build_plan: build: with \SB_CARRY (#1) 174 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Eliminated 0 LUTs. I: glasgow.hardware.build_plan: build: Combined 24 LUTs. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.45. Executing TECHMAP pass (map to technology primitives). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.45.1. Executing Verilog-2005 frontend: /share/ice40/cells_map.v I: glasgow.hardware.build_plan: build: Parsing Verilog input from `/share/ice40/cells_map.v' to AST representation. I: glasgow.hardware.build_plan: build: Generating RTLIL representation for module `\$lut'. I: glasgow.hardware.build_plan: build: Successfully finished Verilog frontend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.45.2. Continuing TECHMAP pass. I: glasgow.hardware.build_plan: build: Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$a59507d273cd827eb6c46c37820d50a1b717efdf\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$d2b5e7b5429639878c0a614cf001753581eebd9c\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$310dc7912bb5756ab08137f6868c0abbecf66466\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$fe7077462a386258cea7b409718bda7873cfae08\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$81222ef5610a5fda47edb055a14a06ce3f531e9d\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$4e9e23686d07a1fd91232ab07371e48a0e62a680\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$6e3b22478ca21c5590744f2e30b92938c4d90996\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111110 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$7b76f914a9a7b5985f645628ce3b7d04e0dd84ea\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010101 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$3f4322953926f7610dcb19ae66f4ff222337de20\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$f5d1c5d5f77f45ffe17befc28ba399e703b6f0a5\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$1c2286bef9a6702a426ede0fc9afc3ceab10d154\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$7417d5c14ea88af43c40449968b06e971c31e1c3\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$474e736e3c2be1c5c72ef98199ca0c7937f8ee13\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$4da6fe9957da309dc16b8f31a6b80b19c05c808d\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$9888082d13c544afa98b0a3109ddbbdba5c4f025\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110110 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$df18ce4400bd5e34c48ef3e0d6f3bee1ca991cf1\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$d5841602ab17202e972b290147d14b63f75b0ad1\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$7b082453f8f50d473c2ca98926eb119a6094bfa4\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$05ac1639ab7543654a2476d11c1711de01f760e6\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$19e5b38cca183d8b6b3a15d20dc995c09cd71893\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$255b0049df4cb49b23955e4a3117758a889578dd\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$2953feb5e102bcccc236b4c0e38de7253e9dd640\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut. I: glasgow.hardware.build_plan: build: No more expansions possible. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Removed 0 unused cells and 1342 unused wires. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.46. Executing AUTONAME pass. I: glasgow.hardware.build_plan: build: Renamed 9201 objects in module top (42 iterations). I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.47. Executing HIERARCHY pass (managing design hierarchy). I: glasgow.hardware.build_plan: build: Attribute `top' found on module `top'. Setting top module to top. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.47.1. Analyzing design hierarchy.. I: glasgow.hardware.build_plan: build: Top module: \top I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.47.2. Analyzing design hierarchy.. I: glasgow.hardware.build_plan: build: Top module: \top I: glasgow.hardware.build_plan: build: Removed 0 unused modules. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.48. Printing statistics. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: === top === I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Number of wires: 1427 I: glasgow.hardware.build_plan: build: Number of wire bits: 2674 I: glasgow.hardware.build_plan: build: Number of public wires: 1427 I: glasgow.hardware.build_plan: build: Number of public wire bits: 2674 I: glasgow.hardware.build_plan: build: Number of ports: 48 I: glasgow.hardware.build_plan: build: Number of port bits: 60 I: glasgow.hardware.build_plan: build: Number of memories: 0 I: glasgow.hardware.build_plan: build: Number of memory bits: 0 I: glasgow.hardware.build_plan: build: Number of processes: 0 I: glasgow.hardware.build_plan: build: Number of cells: 1379 I: glasgow.hardware.build_plan: build: $scopeinfo 90 I: glasgow.hardware.build_plan: build: SB_CARRY 174 I: glasgow.hardware.build_plan: build: SB_DFF 31 I: glasgow.hardware.build_plan: build: SB_DFFE 20 I: glasgow.hardware.build_plan: build: SB_DFFESR 355 I: glasgow.hardware.build_plan: build: SB_DFFSR 11 I: glasgow.hardware.build_plan: build: SB_GB_IO 1 I: glasgow.hardware.build_plan: build: SB_IO 59 I: glasgow.hardware.build_plan: build: SB_LUT4 637 I: glasgow.hardware.build_plan: build: SB_RAM40_4K 1 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 2.49. Executing CHECK pass (checking for obvious problems). I: glasgow.hardware.build_plan: build: Checking module top... I: glasgow.hardware.build_plan: build: Found and reported 0 problems. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: 3. Executing JSON backend. I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: End of script. Logfile hash: 917b278e13, CPU: user 3.11s system 0.00s I: glasgow.hardware.build_plan: build: Yosys 0.53 (git sha1 53c22ab7c, ccache clang 18.1.3 -O3 -flto -flto) I: glasgow.hardware.build_plan: build: Time spent: 32% 11x techmap (1 sec), 29% 19x read_verilog (0 sec), ... I: glasgow.hardware.build_plan: build: + /home/galibert/.local/pipx/venvs/glasgow/bin/yowasp-nextpnr-ice40 --placer heap --log top.tim --hx8k --package bg121 --json top.json --pcf top.pcf --asc top.asc I: glasgow.hardware.build_plan: build: Info: constrained 'i2c_0__scl__io' to bel 'X29/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'i2c_0__sda__io' to bel 'X22/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fifoadr__io[0]' to bel 'X7/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fifoadr__io[1]' to bel 'X6/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__sloe__io' to bel 'X11/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__slrd__io' to bel 'X15/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__slwr__io' to bel 'X8/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__pktend__io' to bel 'X4/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[0]' to bel 'X20/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[1]' to bel 'X20/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[2]' to bel 'X30/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[3]' to bel 'X31/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[4]' to bel 'X31/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[5]' to bel 'X30/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[6]' to bel 'X29/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__fd__io[7]' to bel 'X21/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__flag__io[0]' to bel 'X24/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__flag__io[1]' to bel 'X15/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__flag__io[2]' to bel 'X12/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'fx2_0__flag__io[3]' to bel 'X4/Y0/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_0__io__io' to bel 'X2/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_0__oe__io' to bel 'X20/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_1__io__io' to bel 'X3/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_1__oe__io' to bel 'X26/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_2__io__io' to bel 'X4/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_2__oe__io' to bel 'X25/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_7__io__io' to bel 'X11/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_7__oe__io' to bel 'X26/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_0__io__io' to bel 'X33/Y28/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_0__oe__io' to bel 'X33/Y15/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_1__io__io' to bel 'X33/Y27/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_1__oe__io' to bel 'X33/Y11/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_2__io__io' to bel 'X33/Y24/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_2__oe__io' to bel 'X33/Y6/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_3__io__io' to bel 'X33/Y23/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_3__oe__io' to bel 'X33/Y6/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_4__io__io' to bel 'X33/Y17/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_4__oe__io' to bel 'X33/Y4/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_5__io__io' to bel 'X33/Y21/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_5__oe__io' to bel 'X33/Y3/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_6__io__io' to bel 'X33/Y16/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_6__oe__io' to bel 'X33/Y5/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_7__io__io' to bel 'X33/Y14/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_b_7__oe__io' to bel 'X33/Y4/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_s_0__io__io' to bel 'X31/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_s_0__oe__io' to bel 'X5/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'unused_0__io[0]' to bel 'X11/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'unused_0__io[1]' to bel 'X10/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_5__io__io' to bel 'X9/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_5__oe__io' to bel 'X20/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_4__io__io' to bel 'X16/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_4__oe__io' to bel 'X27/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_6__io__io' to bel 'X17/Y33/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'port_a_6__oe__io' to bel 'X28/Y33/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'clk_if_0__io' to bel 'X17/Y0/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'led_0__io' to bel 'X33/Y10/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'led_1__io' to bel 'X33/Y5/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'led_2__io' to bel 'X33/Y19/io1' I: glasgow.hardware.build_plan: build: Info: constrained 'led_3__io' to bel 'X33/Y21/io0' I: glasgow.hardware.build_plan: build: Info: constrained 'led_4__io' to bel 'X33/Y20/io1' I: glasgow.hardware.build_plan: build: Info: constraining clock net 'clk_if_0__io' to 48.00 MHz I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Packing constants.. I: glasgow.hardware.build_plan: build: Info: Packing IOs.. I: glasgow.hardware.build_plan: build: Info: fx2_0__pktend__io feeds SB_IO fx2_crossbar.bus.pktend.buf0, removing $nextpnr_iobuf fx2_0__pktend__io. I: glasgow.hardware.build_plan: build: Info: fx2_0__flag__io[3] feeds SB_IO fx2_crossbar.bus.flag$40.buf3, removing $nextpnr_iobuf fx2_0__flag__io[3]. I: glasgow.hardware.build_plan: build: Info: fx2_0__flag__io[2] feeds SB_IO fx2_crossbar.bus.flag$40.buf2, removing $nextpnr_iobuf fx2_0__flag__io[2]. I: glasgow.hardware.build_plan: build: Info: fx2_0__flag__io[1] feeds SB_IO fx2_crossbar.bus.flag$40.buf1, removing $nextpnr_iobuf fx2_0__flag__io[1]. I: glasgow.hardware.build_plan: build: Info: fx2_0__flag__io[0] feeds SB_IO fx2_crossbar.bus.flag$40.buf0, removing $nextpnr_iobuf fx2_0__flag__io[0]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fifoadr__io[1] feeds SB_IO fx2_crossbar.bus.fifoadr.buf1, removing $nextpnr_iobuf fx2_0__fifoadr__io[1]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fifoadr__io[0] feeds SB_IO fx2_crossbar.bus.fifoadr.buf0, removing $nextpnr_iobuf fx2_0__fifoadr__io[0]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[7] feeds SB_IO fx2_crossbar.bus.fd.buf7, removing $nextpnr_iobuf fx2_0__fd__io[7]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[6] feeds SB_IO fx2_crossbar.bus.fd.buf6, removing $nextpnr_iobuf fx2_0__fd__io[6]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[5] feeds SB_IO fx2_crossbar.bus.fd.buf5, removing $nextpnr_iobuf fx2_0__fd__io[5]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[4] feeds SB_IO fx2_crossbar.bus.fd.buf4, removing $nextpnr_iobuf fx2_0__fd__io[4]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[3] feeds SB_IO fx2_crossbar.bus.fd.buf3, removing $nextpnr_iobuf fx2_0__fd__io[3]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[2] feeds SB_IO fx2_crossbar.bus.fd.buf2, removing $nextpnr_iobuf fx2_0__fd__io[2]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[1] feeds SB_IO fx2_crossbar.bus.fd.buf1, removing $nextpnr_iobuf fx2_0__fd__io[1]. I: glasgow.hardware.build_plan: build: Info: fx2_0__fd__io[0] feeds SB_IO fx2_crossbar.bus.fd.buf0, removing $nextpnr_iobuf fx2_0__fd__io[0]. I: glasgow.hardware.build_plan: build: Info: clk_if_0__io feeds SB_IO cd_sync.clk_buf.buf0, removing $nextpnr_iobuf clk_if_0__io. I: glasgow.hardware.build_plan: build: Info: unused_0__io[1] feeds SB_IO unused_balls.buf1, removing $nextpnr_iobuf unused_0__io[1]. I: glasgow.hardware.build_plan: build: Info: unused_0__io[0] feeds SB_IO unused_balls.buf0, removing $nextpnr_iobuf unused_0__io[0]. I: glasgow.hardware.build_plan: build: Info: port_s_0__oe__io feeds SB_IO unused_pin_12.oe$10.buf0, removing $nextpnr_iobuf port_s_0__oe__io. I: glasgow.hardware.build_plan: build: Info: port_s_0__io__io feeds SB_IO unused_pin_12.io.buf0, removing $nextpnr_iobuf port_s_0__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_7__oe__io feeds SB_IO unused_pin_11.oe$10.buf0, removing $nextpnr_iobuf port_b_7__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_7__io__io feeds SB_IO unused_pin_11.io.buf0, removing $nextpnr_iobuf port_b_7__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_6__oe__io feeds SB_IO unused_pin_10.oe$10.buf0, removing $nextpnr_iobuf port_b_6__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_6__io__io feeds SB_IO unused_pin_10.io.buf0, removing $nextpnr_iobuf port_b_6__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_5__oe__io feeds SB_IO unused_pin_9.oe$10.buf0, removing $nextpnr_iobuf port_b_5__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_5__io__io feeds SB_IO unused_pin_9.io.buf0, removing $nextpnr_iobuf port_b_5__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_4__oe__io feeds SB_IO unused_pin_8.oe$10.buf0, removing $nextpnr_iobuf port_b_4__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_4__io__io feeds SB_IO unused_pin_8.io.buf0, removing $nextpnr_iobuf port_b_4__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_3__oe__io feeds SB_IO unused_pin_7.oe$10.buf0, removing $nextpnr_iobuf port_b_3__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_3__io__io feeds SB_IO unused_pin_7.io.buf0, removing $nextpnr_iobuf port_b_3__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_2__oe__io feeds SB_IO unused_pin_6.oe$10.buf0, removing $nextpnr_iobuf port_b_2__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_2__io__io feeds SB_IO unused_pin_6.io.buf0, removing $nextpnr_iobuf port_b_2__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_1__oe__io feeds SB_IO unused_pin_5.oe$10.buf0, removing $nextpnr_iobuf port_b_1__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_1__io__io feeds SB_IO unused_pin_5.io.buf0, removing $nextpnr_iobuf port_b_1__io__io. I: glasgow.hardware.build_plan: build: Info: port_b_0__oe__io feeds SB_IO unused_pin_4.oe$10.buf0, removing $nextpnr_iobuf port_b_0__oe__io. I: glasgow.hardware.build_plan: build: Info: port_b_0__io__io feeds SB_IO unused_pin_4.io.buf0, removing $nextpnr_iobuf port_b_0__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_7__oe__io feeds SB_IO unused_pin_3.oe$10.buf0, removing $nextpnr_iobuf port_a_7__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_7__io__io feeds SB_IO unused_pin_3.io.buf0, removing $nextpnr_iobuf port_a_7__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_6__oe__io feeds SB_IO U$18.data_buffer.oe.buf0, removing $nextpnr_iobuf port_a_6__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_6__io__io feeds SB_IO U$18.data_buffer.io.buf0, removing $nextpnr_iobuf port_a_6__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_5__oe__io feeds SB_IO U$18.clk_buffer.oe.buf0, removing $nextpnr_iobuf port_a_5__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_5__io__io feeds SB_IO U$18.clk_buffer.io.buf0, removing $nextpnr_iobuf port_a_5__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_4__oe__io feeds SB_IO U$18.lr_buffer.oe.buf0, removing $nextpnr_iobuf port_a_4__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_4__io__io feeds SB_IO U$18.lr_buffer.io.buf0, removing $nextpnr_iobuf port_a_4__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_2__oe__io feeds SB_IO unused_pin_2.oe$10.buf0, removing $nextpnr_iobuf port_a_2__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_2__io__io feeds SB_IO unused_pin_2.io.buf0, removing $nextpnr_iobuf port_a_2__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_1__oe__io feeds SB_IO unused_pin_1.oe$10.buf0, removing $nextpnr_iobuf port_a_1__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_1__io__io feeds SB_IO unused_pin_1.io.buf0, removing $nextpnr_iobuf port_a_1__io__io. I: glasgow.hardware.build_plan: build: Info: port_a_0__oe__io feeds SB_IO unused_pin_0.oe$10.buf0, removing $nextpnr_iobuf port_a_0__oe__io. I: glasgow.hardware.build_plan: build: Info: port_a_0__io__io feeds SB_IO unused_pin_0.io.buf0, removing $nextpnr_iobuf port_a_0__io__io. I: glasgow.hardware.build_plan: build: Info: led_4__io feeds SB_IO pin_led_4.buf.buf0, removing $nextpnr_iobuf led_4__io. I: glasgow.hardware.build_plan: build: Info: led_3__io feeds SB_IO pin_led_3.buf.buf0, removing $nextpnr_iobuf led_3__io. I: glasgow.hardware.build_plan: build: Info: led_2__io feeds SB_IO pin_led_2.buf.buf0, removing $nextpnr_iobuf led_2__io. I: glasgow.hardware.build_plan: build: Info: led_1__io feeds SB_IO pin_led_1.buf.buf0, removing $nextpnr_iobuf led_1__io. I: glasgow.hardware.build_plan: build: Info: led_0__io feeds SB_IO pin_led_0.buf.buf0, removing $nextpnr_iobuf led_0__io. I: glasgow.hardware.build_plan: build: Info: i2c_0__sda__io feeds SB_IO i2c_target.bus.io_sda.buf0, removing $nextpnr_iobuf i2c_0__sda__io. I: glasgow.hardware.build_plan: build: Info: i2c_0__scl__io feeds SB_IO i2c_target.bus.io_scl.buf0, removing $nextpnr_iobuf i2c_0__scl__io. I: glasgow.hardware.build_plan: build: Info: fx2_0__slwr__io feeds SB_IO fx2_crossbar.bus.slwr$37.buf0, removing $nextpnr_iobuf fx2_0__slwr__io. I: glasgow.hardware.build_plan: build: Info: fx2_0__slrd__io feeds SB_IO fx2_crossbar.bus.slrd$36.buf0, removing $nextpnr_iobuf fx2_0__slrd__io. I: glasgow.hardware.build_plan: build: Info: fx2_0__sloe__io feeds SB_IO fx2_crossbar.bus.sloe$35.buf0, removing $nextpnr_iobuf fx2_0__sloe__io. I: glasgow.hardware.build_plan: build: Info: Packing LUT-FFs.. I: glasgow.hardware.build_plan: build: Info: 291 LCs used as LUT4 only I: glasgow.hardware.build_plan: build: Info: 346 LCs used as LUT4 and DFF I: glasgow.hardware.build_plan: build: Info: Packing non-LUT FFs.. I: glasgow.hardware.build_plan: build: Info: 71 LCs used as DFF only I: glasgow.hardware.build_plan: build: Info: Packing carries.. I: glasgow.hardware.build_plan: build: Info: 2 LCs used as CARRY only I: glasgow.hardware.build_plan: build: Info: Packing indirect carry+LUT pairs... I: glasgow.hardware.build_plan: build: Info: 1 LUTs merged into carry LCs I: glasgow.hardware.build_plan: build: Info: Packing RAMs.. I: glasgow.hardware.build_plan: build: Info: Placing PLLs.. I: glasgow.hardware.build_plan: build: Info: Packing special functions.. I: glasgow.hardware.build_plan: build: Info: Packing PLLs.. I: glasgow.hardware.build_plan: build: Info: Promoting globals.. I: glasgow.hardware.build_plan: build: Info: promoting i2c_registers.data_o_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I2_O[2] [reset] (fanout 297) I: glasgow.hardware.build_plan: build: Info: promoting cd_sync.ready_SB_LUT4_I3_O [reset] (fanout 50) I: glasgow.hardware.build_plan: build: Info: promoting U$18.src_SB_DFFESR_Q_E [cen] (fanout 133) I: glasgow.hardware.build_plan: build: Info: promoting U$18.clk2_SB_LUT4_I2_O[0] [cen] (fanout 129) I: glasgow.hardware.build_plan: build: Info: Constraining chains... I: glasgow.hardware.build_plan: build: Info: 9 LCs used to legalise carry chains. I: glasgow.hardware.build_plan: build: Info: Checksum: 0x5fce98b9 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Device utilisation: I: glasgow.hardware.build_plan: build: Info: ICESTORM_LC: 720/ 7680 9% I: glasgow.hardware.build_plan: build: Info: ICESTORM_RAM: 1/ 32 3% I: glasgow.hardware.build_plan: build: Info: SB_IO: 60/ 256 23% I: glasgow.hardware.build_plan: build: Info: SB_GB: 5/ 8 62% I: glasgow.hardware.build_plan: build: Info: ICESTORM_PLL: 0/ 2 0% I: glasgow.hardware.build_plan: build: Info: SB_WARMBOOT: 0/ 1 0% I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Placed 61 cells based on constraints. I: glasgow.hardware.build_plan: build: Info: Creating initial analytic placement for 542 cells, random placement wirelen = 19585. I: glasgow.hardware.build_plan: build: Info: at initial placer iter 0, wirelen = 1045 I: glasgow.hardware.build_plan: build: Info: at initial placer iter 1, wirelen = 812 I: glasgow.hardware.build_plan: build: Info: at initial placer iter 2, wirelen = 809 I: glasgow.hardware.build_plan: build: Info: at initial placer iter 3, wirelen = 824 I: glasgow.hardware.build_plan: build: Info: Running main analytical placer, max placement attempts per cell = 77224. I: glasgow.hardware.build_plan: build: Info: at iteration #1, type ALL: wirelen solved = 823, spread = 3498, legal = 3876; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #2, type ALL: wirelen solved = 639, spread = 2603, legal = 3261; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #3, type ALL: wirelen solved = 799, spread = 2704, legal = 3011; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #4, type ALL: wirelen solved = 948, spread = 2116, legal = 2681; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #5, type ALL: wirelen solved = 787, spread = 2397, legal = 2974; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #6, type ALL: wirelen solved = 852, spread = 2601, legal = 3236; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #7, type ALL: wirelen solved = 978, spread = 2609, legal = 3245; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #8, type ALL: wirelen solved = 1075, spread = 2992, legal = 3504; time = 0.01s I: glasgow.hardware.build_plan: build: Info: at iteration #9, type ALL: wirelen solved = 1193, spread = 2386, legal = 3405; time = 0.01s I: glasgow.hardware.build_plan: build: Info: HeAP Placer Time: 0.16s I: glasgow.hardware.build_plan: build: Info: of which solving equations: 0.12s I: glasgow.hardware.build_plan: build: Info: of which spreading cells: 0.01s I: glasgow.hardware.build_plan: build: Info: of which strict legalisation: 0.01s I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Running simulated annealing placer for refinement. I: glasgow.hardware.build_plan: build: Info: at iteration #1: temp = 0.000000, timing cost = 40, wirelen = 2681 I: glasgow.hardware.build_plan: build: Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 2179 I: glasgow.hardware.build_plan: build: Info: at iteration #10: temp = 0.000000, timing cost = 30, wirelen = 1935 I: glasgow.hardware.build_plan: build: Info: at iteration #15: temp = 0.000000, timing cost = 29, wirelen = 1817 I: glasgow.hardware.build_plan: build: Info: at iteration #20: temp = 0.000000, timing cost = 29, wirelen = 1749 I: glasgow.hardware.build_plan: build: Info: at iteration #25: temp = 0.000000, timing cost = 29, wirelen = 1688 I: glasgow.hardware.build_plan: build: Info: at iteration #29: temp = 0.000000, timing cost = 29, wirelen = 1665 I: glasgow.hardware.build_plan: build: Info: SA placement time 0.38s I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Max frequency for clock 'applet0_clk': 43.09 MHz (FAIL at 48.00 MHz) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Max delay -> posedge applet0_clk: 1.95 ns I: glasgow.hardware.build_plan: build: Info: Max delay posedge applet0_clk -> : 2.29 ns I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Slack histogram: I: glasgow.hardware.build_plan: build: Info: legend: * represents 8 endpoint(s) I: glasgow.hardware.build_plan: build: Info: + represents [1,8) endpoint(s) I: glasgow.hardware.build_plan: build: Info: [ -2374, -1268) |+ I: glasgow.hardware.build_plan: build: Info: [ -1268, -162) |+ I: glasgow.hardware.build_plan: build: Info: [ -162, 944) |+ I: glasgow.hardware.build_plan: build: Info: [ 944, 2050) |+ I: glasgow.hardware.build_plan: build: Info: [ 2050, 3156) |+ I: glasgow.hardware.build_plan: build: Info: [ 3156, 4262) |+ I: glasgow.hardware.build_plan: build: Info: [ 4262, 5368) |+ I: glasgow.hardware.build_plan: build: Info: [ 5368, 6474) |+ I: glasgow.hardware.build_plan: build: Info: [ 6474, 7580) |+ I: glasgow.hardware.build_plan: build: Info: [ 7580, 8686) |*************+ I: glasgow.hardware.build_plan: build: Info: [ 8686, 9792) |*****+ I: glasgow.hardware.build_plan: build: Info: [ 9792, 10898) |+ I: glasgow.hardware.build_plan: build: Info: [ 10898, 12004) |******+ I: glasgow.hardware.build_plan: build: Info: [ 12004, 13110) |************+ I: glasgow.hardware.build_plan: build: Info: [ 13110, 14216) |******************************+ I: glasgow.hardware.build_plan: build: Info: [ 14216, 15322) |**************************+ I: glasgow.hardware.build_plan: build: Info: [ 15322, 16428) |**********+ I: glasgow.hardware.build_plan: build: Info: [ 16428, 17534) |*******************+ I: glasgow.hardware.build_plan: build: Info: [ 17534, 18640) |*******************************+ I: glasgow.hardware.build_plan: build: Info: [ 18640, 19746) |************************************************************ I: glasgow.hardware.build_plan: build: Info: Checksum: 0x3af72a70 I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Routing.. I: glasgow.hardware.build_plan: build: Info: Setting up routing queue. I: glasgow.hardware.build_plan: build: Info: Routing 2536 arcs. I: glasgow.hardware.build_plan: build: Info: | (re-)routed arcs | delta | remaining| time spent | I: glasgow.hardware.build_plan: build: Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| I: glasgow.hardware.build_plan: build: Info: 1000 | 14 874 | 14 874 | 1552| 0.14 0.14| I: glasgow.hardware.build_plan: build: Info: 2000 | 122 1724 | 108 850 | 684| 0.08 0.22| I: glasgow.hardware.build_plan: build: Info: 2766 | 188 2421 | 66 697 | 0| 0.16 0.38| I: glasgow.hardware.build_plan: build: Info: Routing complete. I: glasgow.hardware.build_plan: build: Info: Router1 time 0.38s I: glasgow.hardware.build_plan: build: Info: Checksum: 0x59b4a1eb I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Critical path report for clock 'applet0_clk' (posedge -> posedge): I: glasgow.hardware.build_plan: build: Info: type curr total name I: glasgow.hardware.build_plan: build: Info: clk-to-q 0.54 0.54 Source U$18.sr_SB_DFFESR_Q_127_D_SB_LUT4_O_LC.O I: glasgow.hardware.build_plan: build: Info: routing 0.59 1.13 Net U$18.sr[0] (16,2) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink $nextpnr_ICESTORM_LC_5.I1 I: glasgow.hardware.build_plan: build: Info: logic 0.26 1.39 Source $nextpnr_ICESTORM_LC_5.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 1.39 Net $nextpnr_ICESTORM_LC_5$O (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_126_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: logic 0.13 1.51 Source U$18.sr_SB_DFFESR_Q_126_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 1.51 Net U$18.sr_SB_DFFESR_Q_125_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_125_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 1.64 Source U$18.sr_SB_DFFESR_Q_125_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 1.64 Net U$18.sr_SB_DFFESR_Q_124_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_124_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 1.76 Source U$18.sr_SB_DFFESR_Q_124_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 1.76 Net U$18.sr_SB_DFFESR_Q_123_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_123_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 1.89 Source U$18.sr_SB_DFFESR_Q_123_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 1.89 Net U$18.sr_SB_DFFESR_Q_122_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_122_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.02 Source U$18.sr_SB_DFFESR_Q_122_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.02 Net U$18.sr_SB_DFFESR_Q_121_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_121_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.14 Source U$18.sr_SB_DFFESR_Q_121_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.14 Net U$18.sr_SB_DFFESR_Q_120_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,1) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_120_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.27 Source U$18.sr_SB_DFFESR_Q_120_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 2.46 Net U$18.sr_SB_DFFESR_Q_119_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,1) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_119_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.59 Source U$18.sr_SB_DFFESR_Q_119_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.59 Net U$18.sr_SB_DFFESR_Q_118_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_118_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.72 Source U$18.sr_SB_DFFESR_Q_118_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.72 Net U$18.sr_SB_DFFESR_Q_117_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_117_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.84 Source U$18.sr_SB_DFFESR_Q_117_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.84 Net U$18.sr_SB_DFFESR_Q_116_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_116_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 2.97 Source U$18.sr_SB_DFFESR_Q_116_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 2.97 Net U$18.sr_SB_DFFESR_Q_115_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_115_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.10 Source U$18.sr_SB_DFFESR_Q_115_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 3.10 Net U$18.sr_SB_DFFESR_Q_114_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_114_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.22 Source U$18.sr_SB_DFFESR_Q_114_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 3.22 Net U$18.sr_SB_DFFESR_Q_113_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_113_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.35 Source U$18.sr_SB_DFFESR_Q_113_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 3.35 Net U$18.sr_SB_DFFESR_Q_112_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,2) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_112_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.47 Source U$18.sr_SB_DFFESR_Q_112_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 3.67 Net U$18.sr_SB_DFFESR_Q_111_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,2) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_111_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.80 Source U$18.sr_SB_DFFESR_Q_111_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 3.80 Net U$18.sr_SB_DFFESR_Q_110_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_110_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 3.92 Source U$18.sr_SB_DFFESR_Q_110_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 3.92 Net U$18.sr_SB_DFFESR_Q_109_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_109_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 4.05 Source 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/share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 4.30 Source U$18.sr_SB_DFFESR_Q_107_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 4.30 Net U$18.sr_SB_DFFESR_Q_106_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_106_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 4.43 Source U$18.sr_SB_DFFESR_Q_106_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 4.43 Net U$18.sr_SB_DFFESR_Q_105_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_105_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 4.55 Source U$18.sr_SB_DFFESR_Q_105_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 4.55 Net U$18.sr_SB_DFFESR_Q_104_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,3) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_104_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 4.68 Source U$18.sr_SB_DFFESR_Q_104_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 4.87 Net U$18.sr_SB_DFFESR_Q_103_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,3) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_103_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.00 Source U$18.sr_SB_DFFESR_Q_103_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.00 Net U$18.sr_SB_DFFESR_Q_102_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_102_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.12 Source U$18.sr_SB_DFFESR_Q_102_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.12 Net U$18.sr_SB_DFFESR_Q_101_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_101_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.25 Source U$18.sr_SB_DFFESR_Q_101_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.25 Net U$18.sr_SB_DFFESR_Q_100_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_100_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.38 Source U$18.sr_SB_DFFESR_Q_100_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.38 Net U$18.sr_SB_DFFESR_Q_99_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_99_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.50 Source U$18.sr_SB_DFFESR_Q_99_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.50 Net U$18.sr_SB_DFFESR_Q_98_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_98_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.63 Source U$18.sr_SB_DFFESR_Q_98_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.63 Net U$18.sr_SB_DFFESR_Q_97_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_97_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.76 Source U$18.sr_SB_DFFESR_Q_97_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 5.76 Net U$18.sr_SB_DFFESR_Q_96_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,4) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_96_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 5.88 Source U$18.sr_SB_DFFESR_Q_96_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 6.08 Net U$18.sr_SB_DFFESR_Q_95_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,4) -> (15,5) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_95_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 6.20 Source U$18.sr_SB_DFFESR_Q_95_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 6.20 Net U$18.sr_SB_DFFESR_Q_94_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,5) -> (15,5) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_94_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 6.33 Source U$18.sr_SB_DFFESR_Q_94_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 6.33 Net U$18.sr_SB_DFFESR_Q_93_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,5) -> (15,5) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_93_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 6.45 Source U$18.sr_SB_DFFESR_Q_93_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 6.45 Net U$18.sr_SB_DFFESR_Q_92_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,5) -> (15,5) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_92_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 6.58 Source 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glasgow.hardware.build_plan: build: Info: logic 0.13 8.29 Source U$18.sr_SB_DFFESR_Q_80_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 8.48 Net U$18.sr_SB_DFFESR_Q_79_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,6) -> (15,7) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_79_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 8.61 Source U$18.sr_SB_DFFESR_Q_79_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 8.61 Net U$18.sr_SB_DFFESR_Q_78_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,7) -> (15,7) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_78_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: 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glasgow.hardware.build_plan: build: Info: logic 0.13 11.02 Source U$18.sr_SB_DFFESR_Q_63_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 11.02 Net U$18.sr_SB_DFFESR_Q_62_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,9) -> (15,9) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_62_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 11.15 Source U$18.sr_SB_DFFESR_Q_62_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 11.15 Net U$18.sr_SB_DFFESR_Q_61_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,9) -> (15,9) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_61_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined 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Info: Sink U$18.sr_SB_DFFESR_Q_54_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 12.35 Source U$18.sr_SB_DFFESR_Q_54_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 12.35 Net U$18.sr_SB_DFFESR_Q_53_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,10) -> (15,10) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_53_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 12.48 Source U$18.sr_SB_DFFESR_Q_53_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 12.48 Net U$18.sr_SB_DFFESR_Q_52_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,10) -> (15,10) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_52_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 12.60 Source U$18.sr_SB_DFFESR_Q_52_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 12.60 Net U$18.sr_SB_DFFESR_Q_51_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,10) -> (15,10) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_51_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: 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glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 12.98 Source U$18.sr_SB_DFFESR_Q_49_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 12.98 Net U$18.sr_SB_DFFESR_Q_48_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,10) -> (15,10) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_48_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 13.10 Source U$18.sr_SB_DFFESR_Q_48_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 13.30 Net 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glasgow.hardware.build_plan: build: Info: logic 0.13 13.55 Source U$18.sr_SB_DFFESR_Q_46_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 13.55 Net U$18.sr_SB_DFFESR_Q_45_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,11) -> (15,11) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_45_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 13.68 Source U$18.sr_SB_DFFESR_Q_45_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 13.68 Net U$18.sr_SB_DFFESR_Q_44_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,11) -> (15,11) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_44_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: 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glasgow.hardware.build_plan: build: Info: logic 0.13 16.09 Source U$18.sr_SB_DFFESR_Q_29_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 16.09 Net U$18.sr_SB_DFFESR_Q_28_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,13) -> (15,13) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_28_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 16.21 Source U$18.sr_SB_DFFESR_Q_28_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 16.21 Net U$18.sr_SB_DFFESR_Q_27_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,13) -> (15,13) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_27_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: 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build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 17.80 Source U$18.sr_SB_DFFESR_Q_17_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 17.80 Net U$18.sr_SB_DFFESR_Q_16_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,14) -> (15,14) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_16_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 17.92 Source U$18.sr_SB_DFFESR_Q_16_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 18.12 Net U$18.sr_SB_DFFESR_Q_15_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,14) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_15_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.24 Source U$18.sr_SB_DFFESR_Q_15_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.24 Net U$18.sr_SB_DFFESR_Q_14_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_14_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.37 Source U$18.sr_SB_DFFESR_Q_14_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.37 Net U$18.sr_SB_DFFESR_Q_13_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_13_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.50 Source U$18.sr_SB_DFFESR_Q_13_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.50 Net U$18.sr_SB_DFFESR_Q_12_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_12_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.62 Source U$18.sr_SB_DFFESR_Q_12_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.62 Net U$18.sr_SB_DFFESR_Q_11_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_11_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.75 Source U$18.sr_SB_DFFESR_Q_11_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.75 Net U$18.sr_SB_DFFESR_Q_10_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_10_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 18.87 Source U$18.sr_SB_DFFESR_Q_10_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 18.87 Net U$18.sr_SB_DFFESR_Q_9_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_9_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.00 Source U$18.sr_SB_DFFESR_Q_9_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.00 Net U$18.sr_SB_DFFESR_Q_8_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,15) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_8_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.12 Source U$18.sr_SB_DFFESR_Q_8_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.20 19.32 Net U$18.sr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,15) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.45 Source U$18.sr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.45 Net U$18.sr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.57 Source U$18.sr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.57 Net U$18.sr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.70 Source U$18.sr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.70 Net U$18.sr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.83 Source U$18.sr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.83 Net U$18.sr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 19.95 Source U$18.sr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.00 19.95 Net U$18.sr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I3 (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.13 20.08 Source U$18.sr_SB_DFFESR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT I: glasgow.hardware.build_plan: build: Info: routing 0.26 20.34 Net U$18.sr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI (15,16) -> (15,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O_LC.I3 I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/arith_map.v:62.5-70.4 I: glasgow.hardware.build_plan: build: Info: /share/ice40/abc9_model.v:4.9-4.11 I: glasgow.hardware.build_plan: build: Info: logic 0.31 20.65 Source U$18.sr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O_LC.O I: glasgow.hardware.build_plan: build: Info: routing 0.59 21.24 Net U$18.sr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2] (15,16) -> (14,16) I: glasgow.hardware.build_plan: build: Info: Sink U$18.sr_SB_DFFESR_Q_1_D_SB_LUT4_O_LC.I3 I: glasgow.hardware.build_plan: build: Info: Defined in: I: glasgow.hardware.build_plan: build: Info: /share/ice40/cells_map.v:6.21-6.22 I: glasgow.hardware.build_plan: build: Info: setup 0.34 21.57 Source U$18.sr_SB_DFFESR_Q_1_D_SB_LUT4_O_LC.I3 I: glasgow.hardware.build_plan: build: Info: 17.20 ns logic, 4.38 ns routing I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Critical path report for cross-domain path '' -> 'posedge applet0_clk': I: glasgow.hardware.build_plan: build: Info: type curr total name I: glasgow.hardware.build_plan: build: Info: source 0.00 0.00 Source i2c_target.bus.io_scl.buf0.D_IN_0 I: glasgow.hardware.build_plan: build: Info: routing 1.96 1.96 Net i2c_target.bus.i (29,0) -> (21,6) I: glasgow.hardware.build_plan: build: Info: Sink i2c_target.bus.U$2.i_SB_LUT4_I3_LC.I3 I: glasgow.hardware.build_plan: build: Info: setup 0.34 2.30 Source i2c_target.bus.U$2.i_SB_LUT4_I3_LC.I3 I: glasgow.hardware.build_plan: build: Info: 0.34 ns logic, 1.96 ns routing I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Critical path report for cross-domain path 'posedge applet0_clk' -> '': I: glasgow.hardware.build_plan: build: Info: type curr total name I: glasgow.hardware.build_plan: build: Info: clk-to-q 0.54 0.54 Source i2c_target.bus.io_sda.oe_SB_DFFESR_Q_D_SB_LUT4_O_LC.O I: glasgow.hardware.build_plan: build: Info: routing 1.70 2.24 Net i2c_target.bus.io_sda.oe (21,10) -> (22,0) I: glasgow.hardware.build_plan: build: Info: Sink i2c_target.bus.io_sda.buf0.OUTPUT_ENABLE I: glasgow.hardware.build_plan: build: Info: 0.54 ns logic, 1.70 ns routing I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: ERROR: Max frequency for clock 'applet0_clk': 46.35 MHz (FAIL at 48.00 MHz) I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Max delay -> posedge applet0_clk: 2.30 ns I: glasgow.hardware.build_plan: build: Info: Max delay posedge applet0_clk -> : 2.24 ns I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Slack histogram: I: glasgow.hardware.build_plan: build: Info: legend: * represents 8 endpoint(s) I: glasgow.hardware.build_plan: build: Info: + represents [1,8) endpoint(s) I: glasgow.hardware.build_plan: build: Info: [ -741, 277) |+ I: glasgow.hardware.build_plan: build: Info: [ 277, 1295) |+ I: glasgow.hardware.build_plan: build: Info: [ 1295, 2313) |+ I: glasgow.hardware.build_plan: build: Info: [ 2313, 3331) |+ I: glasgow.hardware.build_plan: build: Info: [ 3331, 4349) |+ I: glasgow.hardware.build_plan: build: Info: [ 4349, 5367) |+ I: glasgow.hardware.build_plan: build: Info: [ 5367, 6385) |+ I: glasgow.hardware.build_plan: build: Info: [ 6385, 7403) |+ I: glasgow.hardware.build_plan: build: Info: [ 7403, 8421) |+ I: glasgow.hardware.build_plan: build: Info: [ 8421, 9439) |*+ I: glasgow.hardware.build_plan: build: Info: [ 9439, 10457) |+ I: glasgow.hardware.build_plan: build: Info: [ 10457, 11475) |****************+ I: glasgow.hardware.build_plan: build: Info: [ 11475, 12493) |*+ I: glasgow.hardware.build_plan: build: Info: [ 12493, 13511) |****+ I: glasgow.hardware.build_plan: build: Info: [ 13511, 14529) |***********************+ I: glasgow.hardware.build_plan: build: Info: [ 14529, 15547) |*****************************************+ I: glasgow.hardware.build_plan: build: Info: [ 15547, 16565) |*********+ I: glasgow.hardware.build_plan: build: Info: [ 16565, 17583) |*************************+ I: glasgow.hardware.build_plan: build: Info: [ 17583, 18601) |***************************+ I: glasgow.hardware.build_plan: build: Info: [ 18601, 19619) |************************************************************ I: glasgow.hardware.build_plan: build: 0 warnings, 1 error I: glasgow.hardware.build_plan: build: I: glasgow.hardware.build_plan: build: Info: Program finished normally. E: glasgowcontrib.applet.mu: gateware build failed with exit code 1; see build log above for details