another choice excerpt from the timing report:

```
Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source pin_port_a_0__io.port_a_0__io_0.D_IN_0
Info:  0.6  0.6    Net multiplexer_port_a_0__io__i (2,33) -> (2,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut0_LC.I0
Info:  0.4  1.0  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut0_LC.O
Info:  0.6  1.6    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$1 (2,32) -> (2,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut1_LC.I0
Info:  0.4  2.1  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut1_LC.O
Info:  0.6  2.7    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$2 (2,32) -> (3,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut2_LC.I0
Info:  0.4  3.1  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut2_LC.O
Info:  0.6  3.7    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$3 (3,32) -> (3,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut3_LC.I0
Info:  0.4  4.1  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut3_LC.O
Info:  0.9  5.0    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$4 (3,32) -> (5,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut4_LC.I0
Info:  0.4  5.5  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut4_LC.O
Info:  0.6  6.1    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$5 (5,32) -> (6,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut5_LC.I0
Info:  0.4  6.5  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut5_LC.O
Info:  1.2  7.7    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$6 (6,32) -> (11,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut6_LC.I0
Info:  0.4  8.2  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut6_LC.O
Info:  1.2  9.4    Net multiplexer.U$$0.U$$0.bus.rx_clk_delay.o$7 (11,32) -> (15,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut7_LC.I0
Info:  0.4  9.9  Source multiplexer.U$$0.U$$0.bus.rx_clk_delay.lut7_LC.O
Info:  0.6 10.5    Net multiplexer.U$$0.U$$0.rx_clk (15,32) -> (16,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut0_LC.I0
Info:  0.4 10.9  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut0_LC.O
Info:  0.9 11.8    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$1 (16,32) -> (18,32)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut1_LC.I0
Info:  0.4 12.2  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut1_LC.O
Info:  0.6 12.8    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$2 (18,32) -> (18,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut2_LC.I0
Info:  0.4 13.3  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut2_LC.O
Info:  0.6 13.9    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$3 (18,31) -> (18,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut3_LC.I0
Info:  0.4 14.3  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut3_LC.O
Info:  0.6 14.9    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$4 (18,31) -> (18,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut4_LC.I0
Info:  0.4 15.4  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut4_LC.O
Info:  0.6 15.9    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$5 (18,31) -> (18,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut5_LC.I0
Info:  0.4 16.4  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut5_LC.O
Info:  0.6 17.0    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$6 (18,31) -> (17,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut6_LC.I0
Info:  0.4 17.4  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut6_LC.O
Info:  0.6 18.0    Net multiplexer.U$$0.U$$0.bus.tx_clk_delay.o$7 (17,31) -> (17,31)
Info:                Sink multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut7_LC.I0
Info:  0.4 18.5  Source multiplexer.U$$0.U$$0.bus.tx_clk_delay.lut7_LC.O
Info:  1.0 19.4    Net multiplexer_port_a_6__io__o (17,31) -> (17,33)
Info:                Sink pin_port_a_6__io.port_a_6__io_0.D_OUT_0
Info: 7.2 ns logic, 12.3 ns routing
```