wehnelt[m]: > <@_discord_433256551373996042:catircservices.org> I'm having some trouble with using a ``Memory``, in ``elaborate`` in a module I have
> 
> ```
>         lut = Memory(width=self.width, depth=2**self.depth, init=sine_seg)
> 
>         m.submodules.lut_read_port = lut_read_port = lut.read_port(transparent=False)
> 
>         m.d.comb += lut_read_port.addr.eq(self.inp)
>         m.d.comb += self.out.eq(lut_read_port.data)
> ```
> 
> and in a simulator I have 
> 
> ```
>         yield top.inp.eq(40)
>         yield Settle()
>         o = yield top.out
> ```
> 
> and unfortunately, o seems to wind up 0. Am I misusing Memory()?

the default read port domain is "sync"