module top(input clock, output [15:0] count);
  reg [31:0] counter = 0;
  
  always @(posedge clock) begin
    counter <= counter + 1;
  end
  
  reg [31:0] my_mem [256];
  
  always @(posedge clock) begin
    my_mem[counter[7:0]] <= counter;
  end
  
  assign count = my_mem[counter[7:0]][15:0];
endmodule