Which yields the following:
```verilog
    casez (\$3 )
      1'h1:
          \s_axi_rresp$next  = 2'h0;
    endcase
    (* src = "/home/aled/Workspace/rtl/amaranth/amaranth/hdl/xfrm.py:503" *)
    casez (s_axi_aclk_rst)
      1'h1:
          \s_axi_rresp$next  = 2'h0;
    endcase
```
Where `$3` is `~s_axi_aresetn` and I have both ports