dut = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
                               features={"err", "rty", "stall", "lock", "cti", "bte"})

        intr_1 = wishbone.Interface(addr_width=30, data_width=32, granularity=8,
                                    features={"err", "rty"}, path=("intr_1",))
        dut.add(intr_1)
        intr_2 = wishbone.Interface(addr_width=30, data_width=32, granularity=16,
                                    features={"err", "rty", "stall", "lock", "cti",
                                              "bte"},
                                    path=("intr_2",))
        dut.add(intr_2)
        output = verilog.convert(dut, name="arbiter")
        io.open("arbiter.v", "wt").write(output)