anyone familiar with the cortex-m7 MPU knows what's wrong with my uncached region configuration?
```rust
    fn configure_uncached_region(mpu: &mut MPU, region: u32, start: u32, size: u32) {
        assert!(size.is_power_of_two());
        assert!(start % size == 0);
        assert!(region <= 7);

        let n = size.ilog2();

        unsafe {
            mpu.rbar.modify(|w| {
                w
                // ADDR[31:N] - Region base address field : N = log2(region size)
                | (start << n)
                // VALID[4] - Set region
                | (1 << 4)
                // REGION[3:0] - Mpu region field - 0
                | (region << 0)
            });
            mpu.rasr.modify(|w| {
                w
                // XN[28] - Instruction access bit (1 : No Execute)
                | (1 << 28)
                // AP[26:24] - Access Permission (011 : Full Access)
                | (0b011 << 24)
                // (TEX(0b001), S(1), C(0), B(0) : NORMAL / Shareable)
                // TEX[21:19]
                | (0b001 << 19)
                // S[18]
                | (1 << 18)
                // C[17] - C
                | (0 << 17)
                // B[16] - B 
                | (0 << 16)
                // SIZE[5:1] - Actual size = 2^(SIZE + 1) => SIZE = log2(Actual size) - 1 = N - 1
                | ((n - 1) << 1)
                // ENABLE[0] - Region enable bit
                | (1 << 0)
            });
        };
    }

    let mut core = unsafe { cortex_m::Peripherals::steal() };

    configure_uncached_region(&mut core.MPU, 0, shared_data_start, shared_data_size);
    configure_uncached_region(&mut core.MPU, 1, dma_accessible_start, dma_accessible_size);

    unsafe {
        core.MPU.ctrl.modify(|w| {
            w
            // PRIVDEFENA[2] - Use default memory map as background region.
            | (1 << 2)
            // ENABLE[0] - Enable MPU
            | (1 << 0)
        });
    };

    core.SCB.enable_dcache(&mut core.CPUID);
    core.SCB.enable_icache();

```