Could someone explain something to me? I'm using an adaptation of @cr1901's PLL code. I thought the default clock domain was called "sync", so i'm confused why this line ```m.domains.sync = ClockDomain("sync")``` is present from this ```        m.domains.sync = ClockDomain("sync")

        clk_frequency = int(platform.default_clk_constraint.frequency)

        # Values generated by icestorm icepll tool.
        # Given input frequency:       100.000 MHz
        # Requested output frequency:   25.000 MHz
        # Achieved output frequency:    25.000 MHz
        m.submodules += Instance("SB_PLL40_CORE",
            p_FEEDBACK_PATH = "SIMPLE",
            p_PLLOUT_SELECT = "GENCLK",
            p_DIVR = Const(0, 4),
            p_DIVF = Const(111, 7),
            p_DIVQ = Const(101, 3),
            p_FILTER_RANGE = Const(101, 3),

            i_REFERENCECLK = clk_frequency,
            i_BYPASS = Const(0),
            i_RESETB = Const(1),

            o_PLLOUTGLOBAL = ClockSignal("sync"),
            o_LOCK = lock,
        )
```