jfng[m]: > <@jfng:matrix.org> @whitequark:matrix.org 
> > The entire register is always accessed simultaneously. In general, on a 32-bit MCU, I will recommend using a 32-bit CSR bus unless otherwise needed. In this case every access is guaranteed to be 1-cycle, 0-latency. Otherwise the bridge will take 4 cycles to do a register write, which is rarely worth it if you can spend the area.
> 
> This won't work with CSR bridged over WB, if the wishbone has a granularity of 8 bits

not with the current interconnect machinery for sure