Anyway, here's my project
https://github.com/mcclure/analogue-core-template-amaranth-variants/tree/supersaw
both pdm simulate and pdm capture_wav fail
this worked before upgrading amaranth (and i can pinpoint which amaranth i upgraded from)
This project *does* have an oddity, which is that this is that Analogue Pocket project with "no platform"
There's this strange setup here for the clock domains I don't understand
https://github.com/mcclure/analogue-core-template-amaranth-variants/blob/supersaw/src/fpga/amaranth_core/embed_amaranth_core/toplevel.py#L90
however, it does seem to me like the input `clk` https://github.com/mcclure/analogue-core-template-amaranth-variants/blob/supersaw/src/fpga/amaranth_core/embed_amaranth_core/toplevel.py#L49 is only assigned *from*, never *to*