ok so
- I'm not using a proper amaranth platform, due to odd constraints of the Analogue Pocket— I'm using something jury-rigged Catherine courteously set up for me
- As a result, after upgrading to a newer Amaranth, `add_clock` stopped working, due to how `clk` is set up
- When I asked about this before I was recommended to try replacing add_clock with an add_process in which I manually set clock low and high
- I made this change https://github.com/mcclure/analogue-core-template-amaranth/blob/supersaw/src/fpga/amaranth_core/embed_amaranth_core/build.py#L25
- It works for my simulate(), which works with while/run_until
- But for my capture_wav and capture_frame functions (see line 69) it just locks up
- These use:
```
    sim = Simulator(top)
    sim.add_process(simulate_fake_clock_factory(top))
    sim.add_sync_process(bench)
    sim.run()
```
To drive.

add_sync_process is not documented and may not even be public API, so I'm not sure what I should "expect" this code to do.