"Should you discuss it again, I..." <- > <@mabl:matrix.org> Should you discuss it again, I like to throw in one more wrinkle: > > I have recently built a AXI-lite to CSR bus bridge. Unfortunately, the AXI-Lite bus is 32bit wide (by definition) but it includes 4 write-only strobe bits for each byte, indicating if that byte shall be written or not. > > So the CSR bus needs to be 8-bit wide, and I have to compose four CSR bus read/writes per AXI-lite read/write. It seems to me that the whole memory layout and register data structures do not cope well with that arrangement. I would like to have the registers aligned on the 32-bit boundaries. Passing that alignment to the memorymap somewhat works - however, the register write strobe is only emitted on the last byte write of that register range. If you have an 16bit register, alignment will round the size up and the write strobe only triggers once the full 32bits (and hence outside of the register) is written. > > I'm not super experienced in HDL design, so I might very-well have missed something. I just wanted you to keep an open eye for AXI-lite and its strobe bits. AXI(-lite) isn't really different from Wishbone in this regard, byte enables are byte enables