anyway i guess here's my question. the mystery "convert 24-bit rgb data to 12-bit DDR for ARISTOTLE" logic. you say "probably the fact the clock is being fed into that is what's messing things up".

to me, that means one of two things.

(1) My logic is being fed into their logic, quartus is then optimizing that logic, and they're optimizing it in a way that violates an undeclared (external) timing constraint.
(2) That logic runs over several cycles, and I need to make sure I don't do anything until it's done running.

If it's (2), then couldn't I just identify what range of cycles the work is happening over and update my rgb_out outside that period of time?
If it's (1), then… what? I have no choice but to run my clock off a PLL, because a PLL can't be optimized away by quartus?