"Hey! In case someone has some..." <- > <@romancardenas:matrix.org> Hey! In case someone has some spare time. We got a new issue in riscv-rt: https://github.com/rust-embedded/riscv/issues/175 > > Looks like the compiler is printing an (spurious?) error about using a missing mul instruction for riscv32imac targets in debug mode. While it raises an error, it also produces a valid binary. In release, no error is triggered. > > Has anyone noticed something like this? Where should we open an issue to track this? i dont know if that hit you but for esp targets using riscv we had the following problem " riscv targets since Rust nightly-2023-08-08 and the introduction of LLVM-17, rustc (and LLVM) claim to support RISCV ISA 2.1 spec (via the "attributes" section in elf object files) " so are you running in some ISA issues here between 2.0 and 2.1?