I saw some discussion about RAM ports, ASIC RAMs from a few days ago. I have worked on radiation-hardened ASIC SRAM compilers in my previous professional life. So some 2 cents from me.
For ASIC SRAM the most area efficient and highest performant SRAM block is a single port SRAM with the port a read-write port. The most natural is for that port is to be transparent when writing to the port; e.g. the sense amplifiers are enabled in each cycle and will sense the written data during a write cycle. We used RS-flops after the sense amplifier to latch the read data. Single port SRAMs can have an enable signal; in our implementation this was connected to a clock gate that gated the clock for a full cycle. If we would had to support a non-transparent write we would need to introduce extra logic that disabled the sense amplifiers during the write.
If you need to decode two addresses in one cycle you need a bigger SRAM cell (at least 8 transistors rather than 6 transistors per bit cell) making the area bigger. The SRAM will also be slower as the bigger size also means bigger capacitive load on the bit lines. In this case it does not matter that much if the two ports are read/write or both and the clock of each of the ports may be asynchronous.
There is a special case where you have a single read port and single write port. Then these two operations could be pipelined after each other internally and keep one address decoder. In this case the ports need to be synchronous to the same clock. You also gain some speed compared to single port RAM as the write cycle could still be ongoing when the clock starts a new cycle. Due to the latter case the write will always be non-transparent in this case.
So for me it was unnatural to find that there was not a read-write port for the memories in Amaranth/Yosys.
I do understand that for FPGA the provided SRAM capabilities is driven more by providing solution to as much uses cases as possible rather squeezing out the last area and performance.