Ok I've arrived at the following which appears to get what I want:
```python
    def elaborate(platform):
        m = Module()
        m.domains.sync = ClockDomain(reset_less=True)
        m.d.comb += ClockSignal().eq(self.s_axi_aclk)
        ...
        return ResetInserter(~self.s_axi_aresetn)(m)
```
and then requesting both ports on the top level