"> <@firefrommoonlight:matrix.org..." <- > <@romancardenas:matrix.org> I missed I very interesting meeting D: > > Riscv-rt does not have interrupt nor exception macros just because no one implemented them yet. But I kind of like the syntax of firefrommoonlight . > > Additionally, I'm not sure if there is a plan to add a way to tell LLVM that the function is an ISR so it takes care of saving the context etc.? I can't remember, but onsdag once shared a post/discussion regarding this. If so, macros could hide this "complexity" to users there's an RFC open https://github.com/rust-lang/rfcs/pull/3246 for architecture specific interrupt calling conventions, on RISC-V iirc the idea is to treat all registers as callee saved, so they're spilled as needed, and use ``xret`` instead of ``ret`` to return. I'm guessing the `` cortex-m `` `` #[interrupt] `` macro expands to a trampoline, while ``riscv-rt`` comes with a generic trampoline wrapping a call to a default trap handler, so it's up to the user to handle that. ideally if the feature ever lands all you'd need is an ``#[export_name=_TIM2_ISR]`` or something.