Had to do a mux 31->1 to ensure yosys generates a muxf7.
```
module zedboard_top_mux
  (input  gclk,
   input  [7:0] sw,
   input  btnc,
   input  btnd,
   input  btnl,
   input  btnr,
   input  btnu,
   output [7:0] led);

  reg [5:0] sel;
  reg [31:0] vec;

	always @(posedge gclk) begin
		vec = (vec << 8) | sw;
	end

	always @(*) begin
		led = vec[{btnc & btnd & btnl & btnr & btnu}];
	end

endmodule
```