module current_led(rst, clk, count);
  reg tmp4  = 0;
  wire [6:0] tmp1 ;
  wire [6:0] tmp2 ;
  input wire clk;
  output [5:0] count;
  reg [5:0] count = 6'h00;
  reg [5:0] \count$next ;
  input rst;
  wire rst;
  assign tmp2  = count + 1'h1;
  always @(posedge clk)
    count <= \count$next ;
  always @* begin
    if (tmp4 ) begin end
    \count$next  = count;
    casez (rst)
      1'h1:
          \count$next  = 6'h00;
    endcase
  end
  assign tmp1  = tmp2 ;
endmodule