I'm on an stm32f411 and my clock setup looks like this:
```
        rcc.cfgr
            .use_hse(25.MHz())
            .hclk(24u32.MHz())
            .sysclk(SYS_CLK.Hz())
            .pclk1(24.MHz())
            .pclk2(24.MHz())
            .require_pll48clk()
            .freeze()
```