m.d.sync += [
                        # Setup address and data
                        sram_0.a.o.eq(0x00000),
                        sram_0.d.o.eq(0xdead),
                    ]
                    m.next = "WRITE_A2"
                with m.State("WRITE_A2"):
                    m.d.sync += [
                        # Enable CS
                        sram_0.cs.o.eq(0),
                        # Enable lower/upper byte mask
                        sram_0.dm.o[0].eq(0),
                        sram_0.dm.o[1].eq(0),
                    ]
                    m.next = "WRITE_A2a"
                with m.State("WRITE_A2a"):
                    m.d.sync += [
                        # Enable write
                        sram_0.we.o.eq(0),
                    ]
                    m.next = "WRITE_A3"
                with m.State("WRITE_A3"):
                    # Delay
                    m.next = "WRITE_A4"
                with m.State("WRITE_A4"):
                    m.d.sync += [
                        # Disable CS (Data latched on rising edge)
                        sram_0.cs.o.eq(1),
                        # Disable lower/upper byte mask
                        sram_0.dm.o[0].eq(1),
                        sram_0.dm.o[1].eq(1),
                        # Disable write
                        sram_0.we.o.eq(1),
                    ]
                    m.next = "READ_A1"