So again I'm building by transpiling amaranth to verilog and then building in Quartus.
Let's imagine that one of my designs tries to do so many things in a single cycle that it takes longer than one cycle to complete.
How will this express itself?
That is, will I get
* An error in amaranth, when I transpile to verilog?
* An error in quartus, when I compile the verilog?
* It will build successfully and then simply work incorrectly (circuit takes too long to stabilize and expected value semi-sporadically appears one cycle late)?