* It is quite common for chips to have a delay after CS or CS#. The operating frequency of the I/O elements of a SoC cannot keep up with the core frequency, which is why it mostly works without delays.

Linux drivers have this for example:

```
Optional SPI slave node properties:
- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
  select and the start of clock signal, at the start of a transfer.
- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
  signal and deactivating chip select, at the end of a transfer.
```