how does the SVD look like...???

```xml
<field>
  <name>PLL1R</name>
  <description>PLL1 DIVR division factor
This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed.
...</description>
  <bitOffset>24</bitOffset>
  <bitWidth>7</bitWidth>
  <access>read-write</access>
  <enumeratedValues>
    <enumeratedValue>
      <name>B_0x0</name>
      <description>Not allowed</description>
      <value>0x0</value>
    </enumeratedValue>
    <enumeratedValue>
      <name>B_0x1</name>
      <description>pll1_r_ck = vco1_ck / 2 (default after reset)</description>
      <value>0x1</value>
    </enumeratedValue>
    <enumeratedValue>
      <name>B_0x2</name>
      <description>pll1_r_ck = vco1_ck / 3</description>
      <value>0x2</value>
    </enumeratedValue>
    <enumeratedValue>
      <name>B_0x3</name>
      <description>pll1_r_ck = vco1_ck / 4</description>
      <value>0x3</value>
    </enumeratedValue>
    <enumeratedValue>
      <name>B_0x7F</name>
      <description>pll1_r_ck = vco1_ck / 128</description>
      <value>0x7F</value>
    </enumeratedValue>
  </enumeratedValues>
</field>