Ok here is a testcase for my issue, it fails on v0.4.0 (when wiring was introduced) up through the current main:

I am assuming I've either done something very stupid or my environment is messed up so not filing an issue yet but can if that makes things easier to track.

```python
from amaranth import Module, Signal

from amaranth.lib import wiring
from amaranth.lib.wiring import In


class Am2911(wiring.Component):
    notneeded: In(4)

    def __init__(self):
        self.upc = Signal(4)

        super().__init__()

    def elaborate(self, platform):
        m = Module()

        m.d.sync += self.upc.eq(self.upc + 1)

        return m


if __name__ == "__main__":
    failures = 0
    for i in range(128):
        try:
            from amaranth.sim import Simulator

            am2911 = Am2911()

            def test():
                yield am2911.upc.eq(0)

                yield

                # This is where it fails ~60 percent of the time
                assert (yield am2911.upc) == 1

            sim = Simulator(am2911)
            sim.add_clock(1e-6)
            sim.add_sync_process(test)
            sim.run()
        except AssertionError:
            # if failures == 0:
            #     import traceback
            #     print(traceback.format_exc())
            failures += 1
    assert failures == 0 or failures == 128, "We expect this to be deterministic, got {:d} failures".format(
        failures
    )
```