similarly to CDC description in other CDC verification systems -- CDC tool understand what clocks have relationships to what through annotations, and then follows rules to infer what signals are associated with what clocks, and warns on known violations (e.g., D pin of a flop is connected to a signal associated with a clock that is unrelated to the flop's CK pin).  it's even a little easier in Glasgow because the PLL hierarchy is known in advance and can be annotated in external to the applet, and because Amaranth is powerful enough to meaningfully metaprogram hierarchy in ways that Verilog is not good at, Amaranth modules can set waivers and rules (i.e., "always ignore the D pin on the first flop in FFSynchronizer", or "don't worry about the data pins associated internal to a flag synchronizer, because the flag was already brought over with a FFSynchronizer"), and could have non-arcane syntax to say "pins `ext_d[9:0]` are related to clock `ext_clk`".

in the ASIC world, this sort of tooling is helpful of course because the cost of failure is very high.  it's less common in the FPGA world because there is at least a software-like feeling of "eh, just do another spin".  but I am sort of of the opinion that good tooling is *especially* useful for novice FPGA digital designers because there are so many otherwise non-obvious gotchas, on top of the mindset shift from writing imperative programs to designing digital logic; I think we've seen, so far, two issues in the last two days that were most likely resolved by 'synchronize your inputs'!