So… I want to shift a signal right one, but I want to fill the leftmost bit with 1s
I think i can get this by playing with signs, but I also want to do arithmetic on this without getting signed behavior (I'm not sure when that would come up, but if it comes up, I don't want it)
if I do
```
m.d.sync += [
    x.eq(x.shift_right(1)),
    x[most_significant_bit].eq(1)
]
```
Do I get what I want?