"hi, is there any way to specify..." <- > <@_discord_689943776856113163:catircservices.org> hi, is there any way to specify the frequency of the clock of a user-defined clock domain that's 100% internal to the fpga fabric? > > i currently have this design for xilinx 7-series, using an MMCM primitive to generate a lower-frequency clock for some logic. vivado seems to infer the frequency of the clock by itself and uses it to check whether the low-speed design meets the timing constraints. though, is there any way to make this explicit? id imagine that porting it to a different FPGA (using a different primitive & toolchain), or even a vivado update, would make this bit of magic clock constraint discovery break, so id like to have some safeguards here by specifying constraints manually, without having to create a fake pin etc. generally speaking I would recommend relying on the toolchain, since then you don't run the chance of modifying your MMCM settings and then getting a wrong constraint