Question regarding FSMs. if i have a verilog always block that combines some "if" statements and state machine, for example:
```
    always @(posedge clk) begin
        if (!resetn) begin

            ...
            state <= STATE_RESET;

        end else if (valid && !ready && state == STATE_IDLE) begin
            ...
            state <= STATE_INIT;
        ...
        else case (state)
            STATE_IDLE: begin
                ...
            end

            STATE_RESET: begin
                ...
                state <= STATE_IDLE;
            end
            STATE_INIT: begin
                ...
                state <= STATE_START;
            end
    ...    
 ```
 how would i convert this to Amaranth. Amaranth won't allow "with m.If" constructs outside of specific states. it won't allow:
 ```
     with m.If(~self.reset):
        m.d.sync += [
            ...
        ]
        m.next = "RESET"              <----------- ERROR ---------------

    with m.Elif(self.valid & ~self.ready & fsm.ongoing("IDLE")):
        ...
        m.next = "INIT"

    ...
    with m.FSM(reset="RESET") as fsm:
    self.fsm = fsm
    
    with m.State("IDLE"):
        ...

    with m.State("RESET"):
        ...
        m.next = "IDLE"

    with m.State("INIT"):
        ...
        m.next = "START"
```
I get:
```
File "/home/iposthuman/.local/lib/python3.10/site-packages/amaranth/hdl/dsl.py", line 425, in next
    raise SyntaxError("`m.next = <...>` is only permitted inside an FSM state")
amaranth.hdl.dsl.SyntaxError: `m.next = <...>` is only permitted inside an FSM state
```
I'm not sure how to translate this to Amaranth. How would you control fsm state with if statements outside of an FSM state?
I thought of creating some "extra" state but the FSM may be locked onto to another state.
Thoughts?