```
module pll(\out$1 , rst, clk, out);
  input clk;
  wire clk;
  wire o_locked;
  output out;
  wire out;
  output \out$1 ;
  wire \out$1 ;
  input rst;
  wire rst;
  altera_pll #(
    .duty_cycle0("50"),
    .duty_cycle1("50"),
    .fractional_vco_multiplier("false"),
    .number_of_clocks("2"),
    .operation_mode("normal"),
    .output_clock_frequency0("148 MHz"),
    .output_clock_frequency1("1.536 MHz"),
    .phase_shift0("0 ps"),
    .phase_shift1("0 ps"),
    .pll_subtype("General"),
    .pll_type("General"),
    .reference_clock_frequency("50 MHz")
  ) pll (
    .fbclk(1'h1),
    .locked(o_locked),
    .outclk({ \out$1 , out }),
    .refclk(clk),
    .rst(rst)
  );
endmodule
```
Not that unreadable