dirbaio: There's actually some registers missing from Lptim in the metapac, in the official BSP:
```c
/**
  * @brief LPTIMER
  */
typedef struct
{
  __IO uint32_t ISR;           /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
  __IO uint32_t ICR;           /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
  __IO uint32_t DIER;          /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
  __IO uint32_t CFGR;          /*!< LPTIM Configuration register,           Address offset: 0x0C */
  __IO uint32_t CR;            /*!< LPTIM Control register,                 Address offset: 0x10 */
  __IO uint32_t CCR1;          /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
  __IO uint32_t ARR;           /*!< LPTIM Autoreload register,              Address offset: 0x18 */
  __IO uint32_t CNT;           /*!< LPTIM Counter register,                 Address offset: 0x1C */
  __IO uint32_t RESERVED0;     /*!< Reserved,                               Address offset: 0x20 */
  __IO uint32_t CFGR2;         /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
  __IO uint32_t RCR;           /*!< LPTIM Repetition register,              Address offset: 0x28 */
  __IO uint32_t CCMR1;         /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
  __IO uint32_t RESERVED1;     /*!< Reserved,                               Address offset: 0x30 */
  __IO uint32_t CCR2;          /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
} LPTIM_TypeDef;
```
Whereas in the pac, RCR, CCMR1, RESERVED1, and CCR2 are not implemented