FreeKill[m]: > <@larunite:matrix.org> Hi all, just want to pick your embedded brains. On cortex M, if you clear an interrupt flag in a peripheral and then immediately return from IRQ, the IRQ can retrigger due to the various buffers and latencies meaning that the peripheral flag isn't *really* clear.
> 
> I thought we could resolve this by a volatile read of the interrupt enable, but that has now been shown not to work.
> 
> Has anyone got a reliable resolution to this?

Usually the interrupt doesn't clear until the source event is clear. This usually is totally separate from the NVIC itself, I have seen targets where I've had to manually wait in the ISR to avoid retriggers, but it's pretty chip/family specific