* I picture a testbench would then look something like this:
```
def ddr_out_process(clk, i0, i1, o):
yield Passive()

intermediate = 0, 0
while True:
yield Edge(clk, 1)
yield o.eq(intermediate[0])
intermediate = (yield i0), (yield i1)

yield Edge(clk, 0)
yield o.eq(intermediate[1])
```