the generated verilog for the problematic part looks sane:
```verilog
  always @* begin
    \grant_state_0$next  = grant_state_0;
    casez (grant_by_priority)
      1'h1:
          casez (grant_state_0)
            1'h0:
                casez ({ requests[1], bus_busy })
                  2'b?1:
                      /* empty */;
                  2'b1?:
                      \grant_state_0$next  = 1'h1;
                endcase
            1'h1:
                casez ({ requests[0], bus_busy })
                  2'b?1:
                      /* empty */;
                  2'b1?:
                      \grant_state_0$next  = 1'h0;
                endcase
          endcase
    endcase
    casez (rst)
      1'h1:
          \grant_state_0$next  = 1'h0;
    endcase
```