"TL;DR: we maintain custom bare..." <- > <@hegza:matrix.org> TL;DR: we maintain custom bare metal rv32emc target for Rust compiler. We'd like it upstreamed. > > We've been developing a RISC-V core for research purposes for some year now. Our core is a RISC-V 32-bit EMC (rv32emc) which is from the Rust compiler's point of view almost exactly the same as rv32imc. Of course there's backend differences and LLVM needs to chime in on the codegen, but the Rust compiler mostly just needs to pick either the +e or the +i flag. Since there's a one-letter difference in the compiler config, we've been maintaining a configuration of the Rust compiler for our own purposes. However, since the Rust compiler config is a bit of a moving target, this is a bit of an undesirable high burden of maintenance for our research org to maintain this configuration and we were thinking of trying to get rv32emc in upstream maintenance. Would this be a good channel to get started on that? you can propose to be included though and there is not a high burden to be added as an Tier3 target. Though its something you would do directly in rust-lang. You can have a look at other PR's that added targets to tier3 or did move them from tier3 to tier2, especially the ones that added the riscv imac support. I assume your target is also a unknown variant, e.g no_std?