they've implemented it in a way that also works across cores even if the other core is one of the riscv ones, at least according to the datasheet.

> The Global Exclusive Monitor enables standard Arm and RISC-V atomic instructions to safely access shared variables in
SRAM from both cores

though you should only do this for sram addresses, not peripheral ram

> Exclusive accesses are only supported on SRAM. The system treats exclusive accesses to other memory regions as
normal reads and writes, reporting exclusivity failure to the originating PE, for example by a non-zero return value from
an Arm strex instruction.