<mabl[m]> "I annotate AXI interfaces like..." <- > <@mabl:matrix.org> I annotate AXI interfaces like this:
> ```
>     def annotate_vivado(self, interface_name: str) -> None:
>         for port_name in list(self.signature.members):
>             port = getattr(self, port_name)
>             port.attrs['X_INTERFACE_INFO'] = f"xilinx.com:interface:aximm:1.0 {interface_name} {port_name}"
> ```
> Where `interface_name` doesn't need to have the same prefix name as the interface. That avoids that vivado autogenerates block diagram names such as "axi_" due to the "__" separator. 
> However, I guess your initial VHDL name problem is not solved by this.

oh, nice, we should have that in -soc eventually imo