m.d.sync += [
                        # Enable CS
                        sram_0.cs.o.eq(0),
                        # Enable lower and upper byte write mask
                        sram_0.dm.o.eq(0b11),
                        # Start driving the bus
                        sram_0.d.oe.eq(1)
                    ]
                    m.next = "WRITE_WE"